From owner-freebsd-questions  Mon Sep  9 06:23:05 1996
Return-Path: owner-questions
Received: (from root@localhost)
          by freefall.freebsd.org (8.7.5/8.7.3) id GAA20204
          for questions-outgoing; Mon, 9 Sep 1996 06:23:05 -0700 (PDT)
Received: from friley216.res.iastate.edu (friley216.res.iastate.edu [129.186.78.216])
          by freefall.freebsd.org (8.7.5/8.7.3) with ESMTP id GAA20198
          for <freebsd-questions@FreeBSD.ORG>; Mon, 9 Sep 1996 06:23:03 -0700 (PDT)
Received: (from ccsanady@localhost) by friley216.res.iastate.edu (8.7.5/8.7.3) id IAA19237 for freebsd-questions@FreeBSD.ORG; Mon, 9 Sep 1996 08:23:02 -0500 (CDT)
Date: Mon, 9 Sep 1996 08:23:02 -0500 (CDT)
From: Chris Csanady <ccsanady@friley216.res.iastate.edu>
Message-Id: <199609091323.IAA19237@friley216.res.iastate.edu>
To: freebsd-questions@FreeBSD.ORG
Subject: Intel SMP cache architecture question..
Sender: owner-questions@FreeBSD.ORG
X-Loop: FreeBSD.org
Precedence: bulk

I am planning on buying a dual proccessor pentium, and I was just curious as
to the way the caching is done.  I recently noticed the lmbench summary on
this list that has the XXpress as having 2 seperate caches, while all others
Ive seen have a single cache.  So on the single cache boards.. are they
split logically?

Well, I dont have too much money, so I'll probably end up going with the Tyan
tomcat II.. unless someone would like to point out that it doesnt work at all.
;)

Laters,
chris