From owner-svn-src-all@freebsd.org Wed Jul 8 13:53:00 2015 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id BB7FA995D49; Wed, 8 Jul 2015 13:53:00 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A0B961A44; Wed, 8 Jul 2015 13:53:00 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.14.9/8.14.9) with ESMTP id t68Dr050028389; Wed, 8 Jul 2015 13:53:00 GMT (envelope-from zbb@FreeBSD.org) Received: (from zbb@localhost) by repo.freebsd.org (8.14.9/8.14.9/Submit) id t68Dr0up028388; Wed, 8 Jul 2015 13:53:00 GMT (envelope-from zbb@FreeBSD.org) Message-Id: <201507081353.t68Dr0up028388@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: zbb set sender to zbb@FreeBSD.org using -f From: Zbigniew Bodek Date: Wed, 8 Jul 2015 13:53:00 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r285270 - head/sys/sys X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Jul 2015 13:53:00 -0000 Author: zbb Date: Wed Jul 8 13:52:59 2015 New Revision: 285270 URL: https://svnweb.freebsd.org/changeset/base/285270 Log: Add memory barrier to bus_dmamap_sync() On platforms which are fully IO-coherent, the map might be null. We need to guarantee that all data is observable after the sync operation is called. Add a memory barrier to ensure that on ARM. Reviewed by: andrew, kib Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3012 Modified: head/sys/sys/bus_dma.h Modified: head/sys/sys/bus_dma.h ============================================================================== --- head/sys/sys/bus_dma.h Wed Jul 8 13:19:13 2015 (r285269) +++ head/sys/sys/bus_dma.h Wed Jul 8 13:52:59 2015 (r285270) @@ -282,13 +282,25 @@ int bus_dmamem_alloc(bus_dma_tag_t dmat, void bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map); /* - * Perform a synchronization operation on the given map. + * Perform a synchronization operation on the given map. If the map + * is NULL we have a fully IO-coherent system. On every ARM architecture + * there must be a memory barrier placed to ensure that all data + * accesses are visible before going any further. */ void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_dmasync_op_t); +#if defined(__arm__) + #define __BUS_DMAMAP_SYNC_DEFAULT mb(); +#elif defined(__aarch64__) + #define __BUS_DMAMAP_SYNC_DEFAULT dmb(sy); +#else + #define __BUS_DMAMAP_SYNC_DEFAULT {} +#endif #define bus_dmamap_sync(dmat, dmamap, op) \ do { \ if ((dmamap) != NULL) \ _bus_dmamap_sync(dmat, dmamap, op); \ + else \ + __BUS_DMAMAP_SYNC_DEFAULT \ } while (0) /*