From owner-freebsd-hackers Mon Nov 25 16:26:29 2002 Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 06CA437B401 for ; Mon, 25 Nov 2002 16:26:28 -0800 (PST) Received: from xorpc.icir.org (xorpc.icir.org [192.150.187.68]) by mx1.FreeBSD.org (Postfix) with ESMTP id 75C1443EAF for ; Mon, 25 Nov 2002 16:26:27 -0800 (PST) (envelope-from rizzo@xorpc.icir.org) Received: from xorpc.icir.org (localhost [127.0.0.1]) by xorpc.icir.org (8.12.3/8.12.3) with ESMTP id gAQ0QGTO056029; Mon, 25 Nov 2002 16:26:16 -0800 (PST) (envelope-from rizzo@xorpc.icir.org) Received: (from rizzo@localhost) by xorpc.icir.org (8.12.3/8.12.3/Submit) id gAQ0QGkr056028; Mon, 25 Nov 2002 16:26:16 -0800 (PST) (envelope-from rizzo) Date: Mon, 25 Nov 2002 16:26:16 -0800 From: Luigi Rizzo To: hackers@freebsd.org Subject: out-of-order execution and code profiling Message-ID: <20021125162615.A52619@xorpc.icir.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i Sender: owner-freebsd-hackers@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG Hi, I just got hit by a peculiar problem related to out-of-order execution of instructions. I was doing some low-level timing measurements using the rdtsc() around selected pieces of code (the rdtsc() is included in the TSTMP() functions that are in RELENG_4, source is in sys/i386/isa/clock.c), as follows: TSTMP(3, ifp->if_unit, 1, 0); tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); TSTMP(3, ifp->if_unit, 2, 0); TSTMP(3, ifp->if_unit, 3, 0); CSR_READ_1() goes to do a volatile read on memory across a 33MHz PCI bus, so it should take a very minimum of 100ns, plus arbitration and bridge crossing and whatnot. To my surprise, on a 750MHz Athlon box, the delta between the first two timestamps turned out to be in the order of 39 clock cycles, whereas the delta between 2 and 3 is the 270-300 cycles range. The only explaination i can find is that the rdtsc() within TSTMP() is executed out of order. I wonder, is there on the high-end i386 processors any 'barrier' instruction of some kind that enforces in-order execution of some piece of code ? cheers luigi To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message