Date: Mon, 23 Feb 2009 09:05:22 -0500 From: John Baldwin <jhb@freebsd.org> To: freebsd-sparc64@freebsd.org Cc: Marius Strobl <marius@alchemy.franken.de> Subject: Re: can anyone make available the whole usIII source tree from perforce please Message-ID: <200902230905.23149.jhb@freebsd.org> In-Reply-To: <20090222170230.GB69979@alchemy.franken.de> References: <1233668470.1364.45.camel@main.lerwick.hopto.org> <499B5520.3040801@kasimir.com> <20090222170230.GB69979@alchemy.franken.de>
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On Sunday 22 February 2009 12:02:30 pm Marius Strobl wrote: > On Wed, Feb 18, 2009 at 01:24:00AM +0100, Florian Smeets wrote: > > On 04.02.2009 15:16 Uhr, Craig Butler wrote: > > >Hi Marius, > > > > > >Thanks for all your hard work and pointers so far. I have compiled and > > >installed the new kernel (cas is statically compiled in). Unfortunately > > >its panic'ing on boot with the following; > > > > > >cas0:<Sun Cassini+ Gigabit Ethernet> at device 10.0 on pci0 > > >panic: trap: memory address not aligned > > >cpuid = 0 > > >Uptime: 1s > > > > > > > FWIW, i compiled a kernel with these changes and the cards probe fine. > > > > cas0: <NS DP83065 Saturn Gigabit Ethernet> mem 0x2000000-0x21fffff at > > device 0.0 on pci1 > > miibus1: <MII bus> on cas0 > > cas0: 16kB RX FIFO, 9kB TX FIFO > > cas0: Ethernet address: 00:03:ba:XX:XX:XX > > cas0: [ITHREAD] > > cas1: <NS DP83065 Saturn Gigabit Ethernet> mem 0x2400000-0x25fffff at > > device 1.0 on pci1 > > miibus2: <MII bus> on cas1 > > cas1: 16kB RX FIFO, 9kB TX FIFO > > cas1: Ethernet address: 00:03:ba:XX:XX:XX > > cas1: [ITHREAD] > > > > I don't have a cable connected yet, as the machine is remote, but I'll > > be sure to test it soon. > > > > FYI, the above panic likely isn't a problem of cas(4) but > arises from the fact that the resource of that NIC starts > at 0 according to its BAR, which is somewhat uncommon but > nevertheless should work yet seems to trigger a bug at > some other level. The PCI bus driver assumes a BAR of 0 is an invalid resource. There are many systems that use 0 to disable a BAR. I have no idea if "0" is a magic value to disable an individual BAR in the PCI spec itself, however. -- John Baldwin
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