Date: Wed, 10 Mar 2010 20:54:08 +0000 (UTC) From: Pyun YongHyeon <yongari@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r204978 - head/sys/dev/bge Message-ID: <201003102054.o2AKs8Yd059277@svn.freebsd.org>
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Author: yongari Date: Wed Mar 10 20:54:08 2010 New Revision: 204978 URL: http://svn.freebsd.org/changeset/base/204978 Log: Set maximum read byte count to 2048 for PCI-X BCM5703/5704 devices. Also disable relaxed ordering as recommended by data sheet for PCI-X devices. For PCI-X BCM5704, set maximum outstanding split transactions to 0 as indicated by data sheet. For BCM5703 in PCI-X mode, DMA read watermark should be less than or equal to maximum read byte count configuration. Enforce this limitation in DMA read watermark configuration. Modified: head/sys/dev/bge/if_bge.c Modified: head/sys/dev/bge/if_bge.c ============================================================================== --- head/sys/dev/bge/if_bge.c Wed Mar 10 20:31:30 2010 (r204977) +++ head/sys/dev/bge/if_bge.c Wed Mar 10 20:54:08 2010 (r204978) @@ -1390,6 +1390,15 @@ bge_chipinit(struct bge_softc *sc) dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; + } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { + /* + * In the BCM5703, the DMA read watermark should + * be set to less than or equal to the maximum + * memory read byte count of the PCI-X command + * register. + */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { /* 1536 bytes for read, 384 bytes for write. */ dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | @@ -3170,7 +3179,26 @@ bge_reset(struct bge_softc *sc) pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); pci_write_config(dev, BGE_PCI_CMD, command, 4); write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); - + /* + * Disable PCI-X relaxed ordering to ensure status block update + * comes first than packet buffer DMA. Otherwise driver may + * read stale status block. + */ + if (sc->bge_flags & BGE_FLAG_PCIX) { + devctl = pci_read_config(dev, + sc->bge_pcixcap + PCIXR_COMMAND, 2); + devctl &= ~PCIXM_COMMAND_ERO; + if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { + devctl &= ~PCIXM_COMMAND_MAX_READ; + devctl |= PCIXM_COMMAND_MAX_READ_2048; + } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { + devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | + PCIXM_COMMAND_MAX_READ); + devctl |= PCIXM_COMMAND_MAX_READ_2048; + } + pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, + devctl, 2); + } /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ if (BGE_IS_5714_FAMILY(sc)) { /* This chip disables MSI on reset. */
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