Date: Thu, 5 Oct 2023 15:35:12 GMT From: Emmanuel Vadot <manu@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 801fb66a7e34 - main - dwc: Do not re-invent phy mode type Message-ID: <202310051535.395FZCZO012997@gitrepo.freebsd.org>
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The branch main has been updated by manu: URL: https://cgit.FreeBSD.org/src/commit/?id=801fb66a7e34c340f23d82f2b375feee4bd87df4 commit 801fb66a7e34c340f23d82f2b375feee4bd87df4 Author: Emmanuel Vadot <manu@FreeBSD.org> AuthorDate: 2023-10-04 16:29:11 +0000 Commit: Emmanuel Vadot <manu@FreeBSD.org> CommitDate: 2023-10-05 15:34:40 +0000 dwc: Do not re-invent phy mode type Directly uses the MII_CONTYPE_* No functional changes intended. --- sys/dev/dwc/dwc1000_reg.h | 5 ----- sys/dev/dwc/if_dwc.c | 8 ++------ sys/dev/dwc/if_dwc_aw.c | 9 +++++++-- sys/dev/dwc/if_dwc_rk.c | 24 ++++++++++++++++-------- 4 files changed, 25 insertions(+), 21 deletions(-) diff --git a/sys/dev/dwc/dwc1000_reg.h b/sys/dev/dwc/dwc1000_reg.h index 1f0957b688ac..40ba8156ea5d 100644 --- a/sys/dev/dwc/dwc1000_reg.h +++ b/sys/dev/dwc/dwc1000_reg.h @@ -34,11 +34,6 @@ #ifndef __DWC1000_REG_H__ #define __DWC1000_REG_H__ -#define PHY_MODE_UNKNOWN 0x0 -#define PHY_MODE_RMII 0x1 -#define PHY_MODE_RGMII 0x2 -#define PHY_MODE_MII 0x3 - #define MAC_CONFIGURATION 0x0 #define CONF_JD (1 << 22) /* jabber timer disable */ #define CONF_BE (1 << 21) /* Frame Burst Enable */ diff --git a/sys/dev/dwc/if_dwc.c b/sys/dev/dwc/if_dwc.c index 0e18d57a4c23..58e4d3cd5a6b 100644 --- a/sys/dev/dwc/if_dwc.c +++ b/sys/dev/dwc/if_dwc.c @@ -509,18 +509,14 @@ dwc_attach(device_t dev) sc->mactype = IF_DWC_MAC_TYPE(dev); sc->node = ofw_bus_get_node(dev); - switch (mii_fdt_get_contype(sc->node)) { + sc->phy_mode = mii_fdt_get_contype(sc->node); + switch (sc->phy_mode) { case MII_CONTYPE_RGMII: case MII_CONTYPE_RGMII_ID: case MII_CONTYPE_RGMII_RXID: case MII_CONTYPE_RGMII_TXID: - sc->phy_mode = PHY_MODE_RGMII; - break; case MII_CONTYPE_RMII: - sc->phy_mode = PHY_MODE_RMII; - break; case MII_CONTYPE_MII: - sc->phy_mode = PHY_MODE_MII; break; default: device_printf(dev, "Unsupported MII type\n"); diff --git a/sys/dev/dwc/if_dwc_aw.c b/sys/dev/dwc/if_dwc_aw.c index e6cf30f91fc3..5ad1d14b385b 100644 --- a/sys/dev/dwc/if_dwc_aw.c +++ b/sys/dev/dwc/if_dwc_aw.c @@ -36,6 +36,8 @@ #include <machine/bus.h> +#include <dev/mii/miivar.h> + #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -76,10 +78,13 @@ a20_if_dwc_init(device_t dev) /* Configure PHY for MII or RGMII mode */ switch(sc->phy_mode) { - case PHY_MODE_RGMII: + case MII_CONTYPE_RGMII: + case MII_CONTYPE_RGMII_ID: + case MII_CONTYPE_RGMII_RXID: + case MII_CONTYPE_RGMII_TXID: tx_parent_name = "gmac_int_tx"; break; - case PHY_MODE_MII: + case MII_CONTYPE_MII: tx_parent_name = "mii_phy_tx"; break; default: diff --git a/sys/dev/dwc/if_dwc_rk.c b/sys/dev/dwc/if_dwc_rk.c index d05352a27793..51edd2450b42 100644 --- a/sys/dev/dwc/if_dwc_rk.c +++ b/sys/dev/dwc/if_dwc_rk.c @@ -38,6 +38,8 @@ #include <net/if.h> #include <net/if_media.h> +#include <dev/mii/miivar.h> + #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -175,7 +177,7 @@ rk3328_set_delays(struct if_dwc_rk_softc *sc) uint32_t reg; uint32_t tx, rx; - if (sc->base.phy_mode != PHY_MODE_RGMII) + if (!mii_contype_is_rgmii(sc->base.phy_mode)) return; reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON0); @@ -210,7 +212,10 @@ rk3328_set_speed(struct if_dwc_rk_softc *sc, int speed) uint32_t reg; switch (sc->base.phy_mode) { - case PHY_MODE_RGMII: + case MII_CONTYPE_RGMII: + case MII_CONTYPE_RGMII_ID: + case MII_CONTYPE_RGMII_RXID: + case MII_CONTYPE_RGMII_TXID: switch (speed) { case IFM_1000_T: case IFM_1000_SX: @@ -230,7 +235,7 @@ rk3328_set_speed(struct if_dwc_rk_softc *sc, int speed) SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1, ((MAC_CON1_GMAC2IO_GMII_CLK_SEL_MASK << 16) | reg)); break; - case PHY_MODE_RMII: + case MII_CONTYPE_RMII: switch (speed) { case IFM_100_TX: reg = MAC_CON1_GMAC2IO_RMII_CLK_SEL_25 | @@ -260,12 +265,15 @@ rk3328_set_phy_mode(struct if_dwc_rk_softc *sc) { switch (sc->base.phy_mode) { - case PHY_MODE_RGMII: + case MII_CONTYPE_RGMII: + case MII_CONTYPE_RGMII_ID: + case MII_CONTYPE_RGMII_RXID: + case MII_CONTYPE_RGMII_TXID: SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1, ((MAC_CON1_GMAC2IO_INTF_SEL_MASK | MAC_CON1_GMAC2IO_RMII_MODE_MASK) << 16) | MAC_CON1_GMAC2IO_INTF_RGMII); break; - case PHY_MODE_RMII: + case MII_CONTYPE_RMII: SYSCON_WRITE_4(sc->grf, sc->integrated_phy ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1, ((MAC_CON1_GMAC2IO_INTF_SEL_MASK | MAC_CON1_GMAC2IO_RMII_MODE_MASK) << 16) | MAC_CON1_GMAC2IO_INTF_RMII | MAC_CON1_GMAC2IO_RMII_MODE); @@ -286,7 +294,7 @@ rk3399_set_delays(struct if_dwc_rk_softc *sc) { uint32_t reg, tx, rx; - if (sc->base.phy_mode != PHY_MODE_RGMII) + if (!mii_contype_is_rgmii(sc->base.phy_mode)) return; reg = SYSCON_READ_4(sc->grf, RK3399_GRF_SOC_CON6); @@ -416,7 +424,7 @@ if_dwc_rk_init_clocks(device_t dev) /* Optional clock */ clk_get_by_ofw_name(dev, 0, "clk_mac_speed", &sc->clk_mac_speed); - if (sc->base.phy_mode == PHY_MODE_RMII) { + if (sc->base.phy_mode == MII_CONTYPE_RMII) { if (clk_get_by_ofw_name(dev, 0, "mac_clk_rx", &sc->mac_clk_rx) != 0) { device_printf(sc->base.dev, "could not get mac_clk_rx clock\n"); sc->mac_clk_rx = NULL; @@ -448,7 +456,7 @@ if_dwc_rk_init_clocks(device_t dev) } } - if (sc->base.phy_mode == PHY_MODE_RMII) { + if (sc->base.phy_mode == MII_CONTYPE_RMII) { if (sc->mac_clk_rx) clk_enable(sc->mac_clk_rx); if (sc->clk_mac_ref)
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