From owner-p4-projects@FreeBSD.ORG Thu Jul 5 11:18:30 2007 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 9754C16A46B; Thu, 5 Jul 2007 11:18:30 +0000 (UTC) X-Original-To: perforce@FreeBSD.org Delivered-To: perforce@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 5455016A469 for ; Thu, 5 Jul 2007 11:18:30 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [69.147.83.41]) by mx1.freebsd.org (Postfix) with ESMTP id 44EE513C45D for ; Thu, 5 Jul 2007 11:18:30 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.8/8.13.8) with ESMTP id l65BITg5049555 for ; Thu, 5 Jul 2007 11:18:29 GMT (envelope-from gonzo@FreeBSD.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.8/8.13.8/Submit) id l65BITOC049552 for perforce@freebsd.org; Thu, 5 Jul 2007 11:18:29 GMT (envelope-from gonzo@FreeBSD.org) Date: Thu, 5 Jul 2007 11:18:29 GMT Message-Id: <200707051118.l65BITOC049552@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to gonzo@FreeBSD.org using -f From: Oleksandr Tymoshenko To: Perforce Change Reviews Cc: Subject: PERFORCE change 122941 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jul 2007 11:18:30 -0000 http://perforce.freebsd.org/chv.cgi?CH=122941 Change 122941 by gonzo@gonzo_jeeves on 2007/07/05 11:17:52 o Replace exception_restore_registers with it's content and put setting cp0 status register to delay slot of eret. Otherwise we're getting Address Error exception trying to fetch eret instruction with KSU bit set in status register. Affected files ... .. //depot/projects/mips2/src/sys/mips/mips/swtch.S#12 edit Differences ... ==== //depot/projects/mips2/src/sys/mips/mips/swtch.S#12 (text+ko) ==== @@ -193,7 +193,67 @@ .set noat lw t3, PC_CURTHREAD(t2) lw k1, TD_FRAME(t3) - jal exception_restore_registers - nop + + /* + * Load extended registers into some GPRs, and start unrolling + * the trapframe, putting back the extended registers just + * before we need to restore those GPRs. This doesn't do any + * special ordering like the save_registers routine might, + * but it keeps the flow relatively consistent. + */ + lw a1, TF_REG_EPC(k1) + lw a0, TF_REG_MULHI(k1) + lw v1, TF_REG_MULLO(k1) + + lw ra, TF_REG_RA(k1) + lw t9, TF_REG_T9(k1) + lw t8, TF_REG_T8(k1) + lw ta3, TF_REG_TA3(k1) + lw ta2, TF_REG_TA2(k1) + lw ta1, TF_REG_TA1(k1) + lw ta0, TF_REG_TA0(k1) + lw t3, TF_REG_T3(k1) + lw t2, TF_REG_T2(k1) + lw t1, TF_REG_T1(k1) + lw t0, TF_REG_T0(k1) + + lw s0, TF_REG_S0(k1) + lw s1, TF_REG_S1(k1) + lw s2, TF_REG_S2(k1) + lw s3, TF_REG_S3(k1) + lw s4, TF_REG_S4(k1) + lw s5, TF_REG_S5(k1) + lw s6, TF_REG_S6(k1) + lw s7, TF_REG_S7(k1) + lw s8, TF_REG_S8(k1) + + /* + * Brief interlude. + */ + mtc0 a1, MIPS_COP_0_EXC_PC + mthi a0 + mtlo v1 + + /* + * Now restore the registers we used for scratch, and nearby + * GPRs. + */ + lw a3, TF_REG_A3(k1) + lw a2, TF_REG_A2(k1) + lw a1, TF_REG_A1(k1) + lw a0, TF_REG_A0(k1) + lw v1, TF_REG_V1(k1) + lw v0, TF_REG_V0(k1) + lw gp, TF_REG_GP(k1) + lw sp, TF_REG_SP(k1) + + /* + * We are done with the assembler temporary, restore it, and + * return with it disabled, just in case. + */ + .set noat + lw AT, TF_REG_AST(k1) + lw k1, TF_REG_SR(k1) eret + mtc0 k1, MIPS_COP_0_STATUS END(fork_trampoline)