Date: Wed, 10 Sep 2014 21:37:48 +0000 (UTC) From: John Baldwin <jhb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r271409 - in head/sys: amd64/amd64 i386/i386 i386/include i386/xen pc98/pc98 Message-ID: <201409102137.s8ALbmDK084034@svn.freebsd.org>
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Author: jhb Date: Wed Sep 10 21:37:47 2014 New Revision: 271409 URL: http://svnweb.freebsd.org/changeset/base/271409 Log: MFamd64: Use initializecpu() to set various model-specific registers on AP startup and AP resume (it was already used for BSP startup and BSP resume). - Split code to do one-time probing of cache properties out of initializecpu() and into initializecpucache(). This is called once on the BSP during boot. - Move enable_sse() into initializecpu(). - Call initializecpu() for AP startup instead of enable_sse() and manually frobbing MSR_EFER to enable PG_NX. - Call initializecpu() when an AP resumes. In theory this will now properly re-enable PG_NX in MSR_EFER when resuming a PAE kernel on APs. Modified: head/sys/amd64/amd64/mp_machdep.c head/sys/i386/i386/initcpu.c head/sys/i386/i386/machdep.c head/sys/i386/i386/mp_machdep.c head/sys/i386/include/md_var.h head/sys/i386/xen/mp_machdep.c head/sys/pc98/pc98/machdep.c Modified: head/sys/amd64/amd64/mp_machdep.c ============================================================================== --- head/sys/amd64/amd64/mp_machdep.c Wed Sep 10 21:25:54 2014 (r271408) +++ head/sys/amd64/amd64/mp_machdep.c Wed Sep 10 21:37:47 2014 (r271409) @@ -721,7 +721,7 @@ init_secondary(void) /* set up CPU registers and state */ cpu_setregs(); - /* set up SSE/NX registers */ + /* set up SSE/NX */ initializecpu(); /* set up FPU state on the AP */ Modified: head/sys/i386/i386/initcpu.c ============================================================================== --- head/sys/i386/i386/initcpu.c Wed Sep 10 21:25:54 2014 (r271408) +++ head/sys/i386/i386/initcpu.c Wed Sep 10 21:37:47 2014 (r271409) @@ -457,7 +457,7 @@ init_winchip(void) fcr &= ~(1ULL << 11); /* - * Additioanlly, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. + * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. */ if (CPUID_TO_MODEL(cpu_id) >= 8) fcr |= (1 << 12) | (1 << 19) | (1 << 20); @@ -674,20 +674,6 @@ init_transmeta(void) } #endif -/* - * Initialize CR4 (Control register 4) to enable SSE instructions. - */ -void -enable_sse(void) -{ -#if defined(CPU_ENABLE_SSE) - if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { - load_cr4(rcr4() | CR4_FXSR | CR4_XMM); - cpu_fxsr = hw_instruction_sse = 1; - } -#endif -} - extern int elf32_nxstack; void @@ -811,7 +797,17 @@ initializecpu(void) default: break; } - enable_sse(); +#if defined(CPU_ENABLE_SSE) + if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { + load_cr4(rcr4() | CR4_FXSR | CR4_XMM); + cpu_fxsr = hw_instruction_sse = 1; + } +#endif +} + +void +initializecpucache(void) +{ /* * CPUID with %eax = 1, %ebx returns Modified: head/sys/i386/i386/machdep.c ============================================================================== --- head/sys/i386/i386/machdep.c Wed Sep 10 21:25:54 2014 (r271408) +++ head/sys/i386/i386/machdep.c Wed Sep 10 21:37:47 2014 (r271409) @@ -2753,6 +2753,7 @@ init386(first) setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); initializecpu(); /* Initialize CPU registers */ + initializecpucache(); /* make an initial tss so cpu can get interrupt stack on syscall! */ /* Note: -16 is so we can grow the trapframe if we came from vm86 */ Modified: head/sys/i386/i386/mp_machdep.c ============================================================================== --- head/sys/i386/i386/mp_machdep.c Wed Sep 10 21:25:54 2014 (r271408) +++ head/sys/i386/i386/mp_machdep.c Wed Sep 10 21:37:47 2014 (r271409) @@ -745,25 +745,15 @@ init_secondary(void) /* set up CPU registers and state */ cpu_setregs(); + /* set up SSE/NX */ + initializecpu(); + /* set up FPU state on the AP */ npxinit(); - /* set up SSE registers */ - enable_sse(); - if (cpu_ops.cpu_init) cpu_ops.cpu_init(); -#ifdef PAE - /* Enable the PTE no-execute bit. */ - if ((amd_feature & AMDID_NX) != 0) { - uint64_t msr; - - msr = rdmsr(MSR_EFER) | EFER_NXE; - wrmsr(MSR_EFER, msr); - } -#endif - /* A quick check from sanity claus */ cpuid = PCPU_GET(cpuid); if (PCPU_GET(apic_id) != lapic_id()) { @@ -1528,6 +1518,7 @@ cpususpend_handler(void) } else { npxresume(&susppcbs[cpu]->sp_fpususpend); pmap_init_pat(); + initializecpu(); PCPU_SET(switchtime, 0); PCPU_SET(switchticks, ticks); Modified: head/sys/i386/include/md_var.h ============================================================================== --- head/sys/i386/include/md_var.h Wed Sep 10 21:25:54 2014 (r271408) +++ head/sys/i386/include/md_var.h Wed Sep 10 21:37:47 2014 (r271409) @@ -99,9 +99,9 @@ void doreti_popl_fs_fault(void) __asm(__ void dump_add_page(vm_paddr_t); void dump_drop_page(vm_paddr_t); void finishidentcpu(void); -void enable_sse(void); void fillw(int /*u_short*/ pat, void *base, size_t cnt); void initializecpu(void); +void initializecpucache(void); void i686_pagezero(void *addr); void sse2_pagezero(void *addr); void init_AMD_Elan_sc520(void); Modified: head/sys/i386/xen/mp_machdep.c ============================================================================== --- head/sys/i386/xen/mp_machdep.c Wed Sep 10 21:25:54 2014 (r271408) +++ head/sys/i386/xen/mp_machdep.c Wed Sep 10 21:37:47 2014 (r271409) @@ -598,22 +598,13 @@ init_secondary(void) for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) invlpg(addr); - /* set up FPU state on the AP */ - npxinit(); #if 0 - - /* set up SSE registers */ - enable_sse(); + /* set up SSE/NX */ + initializecpu(); #endif -#if 0 && defined(PAE) - /* Enable the PTE no-execute bit. */ - if ((amd_feature & AMDID_NX) != 0) { - uint64_t msr; - msr = rdmsr(MSR_EFER) | EFER_NXE; - wrmsr(MSR_EFER, msr); - } -#endif + /* set up FPU state on the AP */ + npxinit(); #if 0 /* A quick check from sanity claus */ if (PCPU_GET(apic_id) != lapic_id()) { Modified: head/sys/pc98/pc98/machdep.c ============================================================================== --- head/sys/pc98/pc98/machdep.c Wed Sep 10 21:25:54 2014 (r271408) +++ head/sys/pc98/pc98/machdep.c Wed Sep 10 21:37:47 2014 (r271409) @@ -2315,6 +2315,7 @@ init386(first) setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); initializecpu(); /* Initialize CPU registers */ + initializecpucache(); /* make an initial tss so cpu can get interrupt stack on syscall! */ /* Note: -16 is so we can grow the trapframe if we came from vm86 */
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