From owner-p4-projects@FreeBSD.ORG Fri Dec 5 19:49:52 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 35B711065672; Fri, 5 Dec 2008 19:49:52 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id ED728106564A for ; Fri, 5 Dec 2008 19:49:51 +0000 (UTC) (envelope-from sam@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id DC8B78FC12 for ; Fri, 5 Dec 2008 19:49:51 +0000 (UTC) (envelope-from sam@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id mB5Jnpwi027906 for ; Fri, 5 Dec 2008 19:49:51 GMT (envelope-from sam@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id mB5JnpxV027904 for perforce@freebsd.org; Fri, 5 Dec 2008 19:49:51 GMT (envelope-from sam@freebsd.org) Date: Fri, 5 Dec 2008 19:49:51 GMT Message-Id: <200812051949.mB5JnpxV027904@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to sam@freebsd.org using -f From: Sam Leffler To: Perforce Change Reviews Cc: Subject: PERFORCE change 154135 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Dec 2008 19:49:52 -0000 http://perforce.freebsd.org/chv.cgi?CH=154135 Change 154135 by sam@sam_ebb on 2008/12/05 19:49:32 style stragglers, reduce indentation to stop 80-col overflow, update copyright date Affected files ... .. //depot/projects/vap/sys/arm/xscale/ixp425/ixp425_npe.c#7 edit Differences ... ==== //depot/projects/vap/sys/arm/xscale/ixp425/ixp425_npe.c#7 (text+ko) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2006 Sam Leffler, Errno Consulting + * Copyright (c) 2006-2008 Sam Leffler, Errno Consulting * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -432,11 +432,10 @@ } /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */ if (image->id == NPE_IMAGE_MARKER) { - DPRINTF(sc->sc_dev, - "imageId 0x%08x not found in image library header\n", - imageId); - /* reached end of library, image not found */ - return ESRCH; + DPRINTF(sc->sc_dev, "imageId 0x%08x not found in " + "image library header\n", imageId); + /* reached end of library, image not found */ + return ESRCH; } offset += image->size; } @@ -799,9 +798,8 @@ /* for each physical register in the NPE reg file, write 0 : */ error = npe_physical_reg_write(sc, regAddr, 0, TRUE); if (error != 0) { - DPRINTF(sc->sc_dev, - "%s: cannot write phy reg, error %u\n", - __func__, error); + DPRINTF(sc->sc_dev, "%s: cannot write phy reg," + "error %u\n", __func__, error); npe_cpu_step_restore(sc); return error; /* abort reset */ } @@ -814,17 +812,16 @@ /* set each context's Context Store registers to reset values */ for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++) { /* NOTE that there is no STEVT register for Context 0 */ - if (!(i == 0 && ctxtReg == IX_NPEDL_CTXT_REG_STEVT)) { - regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; - error = npe_ctx_reg_write(sc, i, ctxtReg, - regVal, TRUE); - if (error != 0) { - DPRINTF(sc->sc_dev, - "%s: cannot write ctx reg, error %u\n", - __func__, error); - npe_cpu_step_restore(sc); - return error; /* abort reset */ - } + if (i == 0 && ctxtReg == IX_NPEDL_CTXT_REG_STEVT) + continue; + regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; + error = npe_ctx_reg_write(sc, i, ctxtReg, + regVal, TRUE); + if (error != 0) { + DPRINTF(sc->sc_dev, "%s: cannot write ctx reg," + "error %u\n", __func__, error); + npe_cpu_step_restore(sc); + return error; /* abort reset */ } } } @@ -1156,8 +1153,9 @@ npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) | (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - /* step execution of NPE intruction using Debug Executing Context stack */ - error = npe_cpu_step(sc, npeInstruction, ctxtNum, IX_NPEDL_RD_INSTR_LDUR); + /* step execution of NPE inst using Debug Executing Context stack */ + error = npe_cpu_step(sc, npeInstruction, ctxtNum, + IX_NPEDL_RD_INSTR_LDUR); if (error != 0) { DPRINTF(sc->sc_dev, "%s(0x%x, %u, %u), cannot step, error %d\n", __func__, regAddr, regSize, ctxtNum, error); @@ -1181,8 +1179,10 @@ DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x, %u, %u)\n", __func__, regAddr, regVal, regSize, ctxtNum); if (regSize == IX_NPEDL_REG_SIZE_WORD) { - /* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */ - /* Write upper half-word (short) to |d0|d1| */ + /* + * NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| + * Write upper half-word (short) to |d0|d1| + */ error = npe_logical_reg_write(sc, regAddr, regVal >> IX_NPEDL_REG_SIZE_SHORT, IX_NPEDL_REG_SIZE_SHORT, ctxtNum, verify); @@ -1199,40 +1199,44 @@ switch (regSize) { case IX_NPEDL_REG_SIZE_BYTE: - npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE; - regVal &= 0xff; - break; + npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE; + regVal &= 0xff; + break; case IX_NPEDL_REG_SIZE_SHORT: - npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT; - regVal &= 0xffff; - break; + npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT; + regVal &= 0xffff; + break; default: - return EINVAL; + return EINVAL; } - /* fill dest operand field of instruction with destination reg addr */ + /* fill dest operand field of inst with dest reg addr */ npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - /* fill src operand field of instruction with least-sig 5 bits of val*/ - npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) << - IX_NPEDL_OFFSET_INSTR_SRC); + /* fill src operand field of inst with least-sig 5 bits of val*/ + npeInstruction |= + ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) << + IX_NPEDL_OFFSET_INSTR_SRC); - /* fill coprocessor field of instruction with most-sig 11 bits of val*/ - npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) << - IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA); + /* fill coprocessor field of inst with most-sig 11 bits of val*/ + npeInstruction |= + ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) << + IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA); /* step execution of NPE intruction using Debug ECS */ error = npe_cpu_step(sc, npeInstruction, - ctxtNum, IX_NPEDL_WR_INSTR_LDUR); + ctxtNum, IX_NPEDL_WR_INSTR_LDUR); } if (error != 0) { - DPRINTF(sc->sc_dev, "%s(0x%x, 0x%x, %u, %u), error %u writing reg\n", - __func__, regAddr, regVal, regSize, ctxtNum, error); + DPRINTF(sc->sc_dev, "%s(0x%x, 0x%x, %u, %u), error %u " + "writing reg\n", __func__, regAddr, regVal, regSize, + ctxtNum, error); return error; } if (verify) { uint32_t retRegVal; - error = npe_logical_reg_read(sc, regAddr, regSize, ctxtNum, &retRegVal); + error = npe_logical_reg_read(sc, regAddr, regSize, ctxtNum, + &retRegVal); if (error == 0 && regVal != retRegVal) error = EIO; /* XXX ambiguous */ }