From owner-svn-src-all@FreeBSD.ORG Sat Oct 2 05:38:45 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BB6F7106564A; Sat, 2 Oct 2010 05:38:45 +0000 (UTC) (envelope-from jmallett@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id AA4ED8FC08; Sat, 2 Oct 2010 05:38:45 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o925cjFd028712; Sat, 2 Oct 2010 05:38:45 GMT (envelope-from jmallett@svn.freebsd.org) Received: (from jmallett@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o925cjaI028708; Sat, 2 Oct 2010 05:38:45 GMT (envelope-from jmallett@svn.freebsd.org) Message-Id: <201010020538.o925cjaI028708@svn.freebsd.org> From: Juli Mallett Date: Sat, 2 Oct 2010 05:38:45 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r213345 - head/sys/mips/cavium X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 02 Oct 2010 05:38:45 -0000 Author: jmallett Date: Sat Oct 2 05:38:45 2010 New Revision: 213345 URL: http://svn.freebsd.org/changeset/base/213345 Log: Rather than shifting offsets by three, set register offset to 3. All our bus interface does that's special here now is to use a 64-bit register size. In theory, uart(4) ought to support a regsz as well as regshft and support 64-bit registers directly. Also use the UART class's range rather than a hand-coded 1024 for the address range. Modified: head/sys/mips/cavium/uart_bus_octeonusart.c head/sys/mips/cavium/uart_cpu_octeonusart.c head/sys/mips/cavium/uart_dev_oct16550.c Modified: head/sys/mips/cavium/uart_bus_octeonusart.c ============================================================================== --- head/sys/mips/cavium/uart_bus_octeonusart.c Sat Oct 2 02:46:32 2010 (r213344) +++ head/sys/mips/cavium/uart_bus_octeonusart.c Sat Oct 2 05:38:45 2010 (r213345) @@ -105,11 +105,10 @@ uart_octeon_probe(device_t dev) sc->sc_bas.bst = uart_bus_space_mem; /* * XXX - * RBR isn't really a great base address and it'd be great to not have - * a hard-coded 1024. + * RBR isn't really a great base address. */ - if (bus_space_map(sc->sc_bas.bst, CVMX_MIO_UARTX_RBR(0), 1024, - 0, &sc->sc_bas.bsh) != 0) + if (bus_space_map(sc->sc_bas.bst, CVMX_MIO_UARTX_RBR(0), + uart_getrange(sc->sc_class), 0, &sc->sc_bas.bsh) != 0) return (ENXIO); return (uart_bus_probe(dev, sc->sc_bas.regshft, 0, 0, unit)); } Modified: head/sys/mips/cavium/uart_cpu_octeonusart.c ============================================================================== --- head/sys/mips/cavium/uart_cpu_octeonusart.c Sat Oct 2 02:46:32 2010 (r213344) +++ head/sys/mips/cavium/uart_cpu_octeonusart.c Sat Oct 2 05:38:45 2010 (r213345) @@ -58,56 +58,56 @@ static uint8_t ou_bs_r_1(void *t, bus_space_handle_t handle, bus_size_t offset) { - return (oct_read64(handle + (offset << 3))); + return (oct_read64(handle + offset)); } static uint16_t ou_bs_r_2(void *t, bus_space_handle_t handle, bus_size_t offset) { - return (oct_read64(handle + (offset << 3))); + return (oct_read64(handle + offset)); } static uint32_t ou_bs_r_4(void *t, bus_space_handle_t handle, bus_size_t offset) { - return (oct_read64(handle + (offset << 3))); + return (oct_read64(handle + offset)); } static uint64_t ou_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset) { - return (oct_read64(handle + (offset << 3))); + return (oct_read64(handle + offset)); } static void ou_bs_w_1(void *t, bus_space_handle_t bsh, bus_size_t offset, uint8_t value) { - oct_write64(bsh + (offset << 3), value); + oct_write64(bsh + offset, value); } static void ou_bs_w_2(void *t, bus_space_handle_t bsh, bus_size_t offset, uint16_t value) { - oct_write64(bsh + (offset << 3), value); + oct_write64(bsh + offset, value); } static void ou_bs_w_4(void *t, bus_space_handle_t bsh, bus_size_t offset, uint32_t value) { - oct_write64(bsh + (offset << 3), value); + oct_write64(bsh + offset, value); } static void ou_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset, uint64_t value) { - oct_write64(bsh + (offset << 3), value); + oct_write64(bsh + offset, value); } struct bus_space octeon_uart_tag = { @@ -160,10 +160,10 @@ uart_cpu_getdev(int devtype, struct uart di->ops = uart_getops(class); di->bas.chan = 0; /* XXX */ - if (bus_space_map(di->bas.bst, CVMX_MIO_UARTX_RBR(0), 1024, - 0, &di->bas.bsh) != 0) + if (bus_space_map(di->bas.bst, CVMX_MIO_UARTX_RBR(0), + uart_getrange(class), 0, &di->bas.bsh) != 0) return (ENXIO); - di->bas.regshft = 0; + di->bas.regshft = 3; di->bas.rclk = 0; di->baudrate = 115200; di->databits = 8; Modified: head/sys/mips/cavium/uart_dev_oct16550.c ============================================================================== --- head/sys/mips/cavium/uart_dev_oct16550.c Sat Oct 2 02:46:32 2010 (r213344) +++ head/sys/mips/cavium/uart_dev_oct16550.c Sat Oct 2 05:38:45 2010 (r213345) @@ -420,7 +420,7 @@ struct uart_class uart_oct16550_class = oct16550_methods, sizeof(struct oct16550_softc), .uc_ops = &uart_oct16550_ops, - .uc_range = 8, + .uc_range = 8 << 3, .uc_rclk = 0 };