From owner-svn-src-head@FreeBSD.ORG Sun Aug 25 11:34:38 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 12413D5B; Sun, 25 Aug 2013 11:34:38 +0000 (UTC) (envelope-from dumbbell@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id E50E728C6; Sun, 25 Aug 2013 11:34:37 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r7PBYbQD039892; Sun, 25 Aug 2013 11:34:37 GMT (envelope-from dumbbell@svn.freebsd.org) Received: (from dumbbell@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r7PBYbIG039886; Sun, 25 Aug 2013 11:34:37 GMT (envelope-from dumbbell@svn.freebsd.org) Message-Id: <201308251134.r7PBYbIG039886@svn.freebsd.org> From: Jean-Sebastien Pedron Date: Sun, 25 Aug 2013 11:34:37 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r254848 - head/sys/dev/drm2 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 25 Aug 2013 11:34:38 -0000 Author: dumbbell Date: Sun Aug 25 11:34:37 2013 New Revision: 254848 URL: http://svnweb.freebsd.org/changeset/base/254848 Log: drm: Import drm_pcie_get_speed_cap_mask() in drm_pci.c This comes with several PCI_VENDOR_ID_* defines which should go in a more central place. Modified: head/sys/dev/drm2/drmP.h head/sys/dev/drm2/drm_pci.c Modified: head/sys/dev/drm2/drmP.h ============================================================================== --- head/sys/dev/drm2/drmP.h Sun Aug 25 11:23:38 2013 (r254847) +++ head/sys/dev/drm2/drmP.h Sun Aug 25 11:34:37 2013 (r254848) @@ -1421,5 +1421,22 @@ do { \ #define EREMOTEIO ENXIO #define ERESTARTSYS ERESTART +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_VENDOR_ID_ASUSTEK 0x1043 +#define PCI_VENDOR_ID_ATI 0x1002 +#define PCI_VENDOR_ID_DELL 0x1028 +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_VENDOR_ID_SERVERWORKS 0x1166 +#define PCI_VENDOR_ID_SONY 0x104d +#define PCI_VENDOR_ID_VIA 0x1106 + +#define DRM_PCIE_SPEED_25 1 +#define DRM_PCIE_SPEED_50 2 +#define DRM_PCIE_SPEED_80 4 + +extern int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *speed_mask); + #endif /* __KERNEL__ */ #endif /* _DRM_P_H_ */ Modified: head/sys/dev/drm2/drm_pci.c ============================================================================== --- head/sys/dev/drm2/drm_pci.c Sun Aug 25 11:23:38 2013 (r254847) +++ head/sys/dev/drm2/drm_pci.c Sun Aug 25 11:34:37 2013 (r254848) @@ -123,3 +123,53 @@ drm_pci_free(struct drm_device *dev, drm } /*@}*/ + +int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *mask) +{ + device_t root; + int pos; + u32 lnkcap = 0, lnkcap2 = 0; + + *mask = 0; + if (!drm_device_is_pcie(dev)) + return -EINVAL; + + root = device_get_parent(dev->device); + + pos = 0; + pci_find_cap(root, PCIY_EXPRESS, &pos); + if (!pos) + return -EINVAL; + + /* we've been informed via and serverworks don't make the cut */ + if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || + pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) + return -EINVAL; + + lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); + lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); + + lnkcap &= PCIEM_LINK_CAP_MAX_SPEED; + lnkcap2 &= 0xfe; + +#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ +#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ +#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ + + if (lnkcap2) { /* PCIE GEN 3.0 */ + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) + *mask |= DRM_PCIE_SPEED_25; + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) + *mask |= DRM_PCIE_SPEED_50; + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) + *mask |= DRM_PCIE_SPEED_80; + } else { + if (lnkcap & 1) + *mask |= DRM_PCIE_SPEED_25; + if (lnkcap & 2) + *mask |= DRM_PCIE_SPEED_50; + } + + DRM_INFO("probing gen 2 caps for device %x:%x = %x/%x\n", pci_get_vendor(root), pci_get_device(root), lnkcap, lnkcap2); + return 0; +}