From nobody Fri Apr 28 17:45:08 2023 X-Original-To: freebsd-arch@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Q7Kkk36wRz47m1N for ; Fri, 28 Apr 2023 17:45:18 +0000 (UTC) (envelope-from hps@selasky.org) Received: from mail.turbocat.net (turbocat.net [88.99.82.50]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4Q7Kkj5tfcz4LVD; Fri, 28 Apr 2023 17:45:17 +0000 (UTC) (envelope-from hps@selasky.org) Authentication-Results: mx1.freebsd.org; none Received: from [10.36.2.154] (unknown [46.212.121.255]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by mail.turbocat.net (Postfix) with ESMTPSA id A1DFC2605A4; Fri, 28 Apr 2023 19:45:08 +0200 (CEST) Message-ID: <6079003b-7df2-f3c2-f624-6fe39a1cf9c0@selasky.org> Date: Fri, 28 Apr 2023 19:45:08 +0200 List-Id: Discussion related to FreeBSD architecture List-Archive: https://lists.freebsd.org/archives/freebsd-arch List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-arch@freebsd.org MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: Future of 32-bit platforms (including i386) Content-Language: en-US To: Jessica Clarke Cc: freebsd-arch , John Baldwin References: <671d3bf6-b207-e7c5-5282-4df317193db6@selasky.org> From: Hans Petter Selasky In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 4Q7Kkj5tfcz4LVD X-Spamd-Bar: ---- X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:24940, ipnet:88.99.0.0/16, country:DE] X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-ThisMailContainsUnwantedMimeParts: N On 4/28/23 01:50, Jessica Clarke wrote: > On 28 Apr 2023, at 00:44, Hans Petter Selasky wrote: >> >> On 4/27/23 19:19, John Baldwin wrote: >>> For 13.0, i386 was demoted from Tier 1 to Tier 2. In the announcement >>> of this for 13.0, the project committed to an update on i386's future >>> around the time of 14.0. The announcement at the time suggested that >>> i386 would be supported less in 14.x than in 13.x. >> >> Hi, >> >> This makes me think about all the issues about the "long" type in the past, and printf() and more, being caught when compiling TARGET_ARCH=i386 . >> >> Maybe just put the following line of code somewhere central :-) >> >> _Static_assert(sizeof(long) == 8); >> >> Will there ever be some kind of hybrid CPU systems? >> >> 4 cores AMD64, 4 cores AARCH64 and some virtual QEMU CPUs all running on the same system? >> >> I mean, the arm vs intel battle is not going to end soonish. And emulating CPUs is slow and waste electricity. Why not have one computer having both kind of CPUs, and one OS, and one harddisk? And figure out a common ABI allowing seamless task switching between them? I know there are some hard differences, but can't those be ironed out? > > I don’t know where to start with this other than to give an emphatic no to almost all of what you said, or at least the bits for which meaning can be extracted. Regardless, this is not the place for such pie-in-the-sky discussions; if you want to theorise about weird and wacky computer architectures then please take it elsewhere. > Hi Jess, I'd like to know why you think this is a wacky idea, to have a super-set computer architecture, where each CPU can run the full instruction set of both ARM64 and AARCH64 at the same time. You have an open invitation for a video call on FaceBook or whatever you prefer to talk about this. Send me something off-list. --HPS