From owner-svn-src-head@FreeBSD.ORG Wed Apr 30 14:38:14 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 1EFD886E; Wed, 30 Apr 2014 14:38:14 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id F37481968; Wed, 30 Apr 2014 14:38:13 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s3UEcDIF076884; Wed, 30 Apr 2014 14:38:13 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s3UEcDgP076881; Wed, 30 Apr 2014 14:38:13 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201404301438.s3UEcDgP076881@svn.freebsd.org> From: Ian Lepore Date: Wed, 30 Apr 2014 14:38:13 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r265148 - head/sys/arm/xilinx X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Apr 2014 14:38:14 -0000 Author: ian Date: Wed Apr 30 14:38:13 2014 New Revision: 265148 URL: http://svnweb.freebsd.org/changeset/base/265148 Log: Convert the Zynq SoC support to the new routines for static device mapping. Modified: head/sys/arm/xilinx/zy7_machdep.c head/sys/arm/xilinx/zy7_reg.h Modified: head/sys/arm/xilinx/zy7_machdep.c ============================================================================== --- head/sys/arm/xilinx/zy7_machdep.c Wed Apr 30 14:09:26 2014 (r265147) +++ head/sys/arm/xilinx/zy7_machdep.c Wed Apr 30 14:38:13 2014 (r265148) @@ -60,7 +60,7 @@ vm_offset_t initarm_lastaddr(void) { - return (ZYNQ7_PSIO_VBASE); + return (arm_devmap_lastaddr()); } void @@ -79,39 +79,18 @@ initarm_late_init(void) { } -#define FDT_DEVMAP_SIZE 3 -static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_SIZE]; - /* - * Construct pmap_devmap[] with DT-derived config data. + * Set up static device mappings. Not strictly necessary -- simplebus will + * dynamically establish mappings as needed -- but doing it this way gets us + * nice efficient 1MB section mappings. */ int initarm_devmap_init(void) { - int i = 0; - fdt_devmap[i].pd_va = ZYNQ7_PSIO_VBASE; - fdt_devmap[i].pd_pa = ZYNQ7_PSIO_HWBASE; - fdt_devmap[i].pd_size = ZYNQ7_PSIO_SIZE; - fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; - fdt_devmap[i].pd_cache = PTE_DEVICE; - i++; - - fdt_devmap[i].pd_va = ZYNQ7_PSCTL_VBASE; - fdt_devmap[i].pd_pa = ZYNQ7_PSCTL_HWBASE; - fdt_devmap[i].pd_size = ZYNQ7_PSCTL_SIZE; - fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; - fdt_devmap[i].pd_cache = PTE_DEVICE; - i++; - - /* end of table */ - fdt_devmap[i].pd_va = 0; - fdt_devmap[i].pd_pa = 0; - fdt_devmap[i].pd_size = 0; - fdt_devmap[i].pd_prot = 0; - fdt_devmap[i].pd_cache = 0; + arm_devmap_add_entry(ZYNQ7_PSIO_HWBASE, ZYNQ7_PSIO_SIZE); + arm_devmap_add_entry(ZYNQ7_PSCTL_HWBASE, ZYNQ7_PSCTL_SIZE); - arm_devmap_register_table(&fdt_devmap[0]); return (0); } Modified: head/sys/arm/xilinx/zy7_reg.h ============================================================================== --- head/sys/arm/xilinx/zy7_reg.h Wed Apr 30 14:09:26 2014 (r265147) +++ head/sys/arm/xilinx/zy7_reg.h Wed Apr 30 14:38:13 2014 (r265148) @@ -44,16 +44,13 @@ #define ZYNQ7_PLGP1_SIZE 0x40000000 /* I/O Peripheral registers. */ -#define ZYNQ7_PSIO_VBASE 0xE0000000 #define ZYNQ7_PSIO_HWBASE 0xE0000000 #define ZYNQ7_PSIO_SIZE 0x00300000 /* UART0 and UART1 */ -#define ZYNQ7_UART0_VBASE (ZYNQ7_PSIO_VBASE) #define ZYNQ7_UART0_HWBASE (ZYNQ7_PSIO_HWBASE) #define ZYNQ7_UART0_SIZE 0x1000 -#define ZYNQ7_UART1_VBASE (ZYNQ7_PSIO_VBASE+0x1000) #define ZYNQ7_UART1_HWBASE (ZYNQ7_PSIO_HWBASE+0x1000) #define ZYNQ7_UART1_SIZE 0x1000 @@ -63,15 +60,12 @@ #define ZYNQ7_SMC_SIZE 0x05000000 /* SLCR, PS system, and CPU private registers combined in this region. */ -#define ZYNQ7_PSCTL_VBASE 0xF8000000 #define ZYNQ7_PSCTL_HWBASE 0xF8000000 #define ZYNQ7_PSCTL_SIZE 0x01000000 -#define ZYNQ7_SLCR_VBASE (ZYNQ7_PSCTL_VBASE) #define ZYNQ7_SLCR_HWBASE (ZYNQ7_PSCTL_HWBASE) #define ZYNQ7_SLCR_SIZE 0x1000 -#define ZYNQ7_DEVCFG_VBASE (ZYNQ7_PSCTL_VBASE+0x7000) #define ZYNQ7_DEVCFG_HWBASE (ZYNQ7_PSCTL_HWBASE+0x7000) #define ZYNQ7_DEVCFG_SIZE 0x1000