From owner-freebsd-threads@FreeBSD.ORG Wed Aug 6 12:01:33 2003 Return-Path: Delivered-To: freebsd-threads@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 8F5DE37B401 for ; Wed, 6 Aug 2003 12:01:33 -0700 (PDT) Received: from ns1.xcllnt.net (209-128-86-226.BAYAREA.NET [209.128.86.226]) by mx1.FreeBSD.org (Postfix) with ESMTP id D47D743F3F for ; Wed, 6 Aug 2003 12:01:32 -0700 (PDT) (envelope-from marcel@xcllnt.net) Received: from athlon.pn.xcllnt.net (athlon.pn.xcllnt.net [192.168.4.3]) by ns1.xcllnt.net (8.12.9/8.12.9) with ESMTP id h76J1WwO039372 for ; Wed, 6 Aug 2003 12:01:32 -0700 (PDT) (envelope-from marcel@piii.pn.xcllnt.net) Received: from athlon.pn.xcllnt.net (localhost [127.0.0.1]) by athlon.pn.xcllnt.net (8.12.9/8.12.9) with ESMTP id h76J1WG0001001 for ; Wed, 6 Aug 2003 12:01:32 -0700 (PDT) (envelope-from marcel@athlon.pn.xcllnt.net) Received: (from marcel@localhost) by athlon.pn.xcllnt.net (8.12.9/8.12.9/Submit) id h76J1WMY001000 for threads@freebsd.org; Wed, 6 Aug 2003 12:01:32 -0700 (PDT) (envelope-from marcel) Date: Wed, 6 Aug 2003 12:01:32 -0700 From: Marcel Moolenaar To: threads@freebsd.org Message-ID: <20030806190132.GB893@athlon.pn.xcllnt.net> References: <20030806185530.GA893@athlon.pn.xcllnt.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20030806185530.GA893@athlon.pn.xcllnt.net> User-Agent: Mutt/1.5.4i Subject: Re: KSE/ia64: a quick update X-BeenThere: freebsd-threads@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Threading on FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Aug 2003 19:01:33 -0000 On Wed, Aug 06, 2003 at 11:55:30AM -0700, Marcel Moolenaar wrote: > About the high FP: > > On ia64 the FP registers are split in two (2) sets: low and high. > Both sets can be enabled and disabled independently from each other > and each set has a modified bit to keep track of usage. The low > FP registers are f0-f31 and are always enabled. The high FP registers > are f32-f127 and are disabled by default. We use lazy context > switching to save and restore these on a need to have basis. When ^^^^^ These applies to the high FP registers only. We put the low FP registers in the trapframe or PCB. Only the high FP registers are lazily switched. -- Marcel Moolenaar USPA: A-39004 marcel@xcllnt.net