From owner-svn-src-all@FreeBSD.ORG Thu Aug 12 11:00:45 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id CC3621065697; Thu, 12 Aug 2010 11:00:45 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id BAE8B8FC17; Thu, 12 Aug 2010 11:00:45 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o7CB0jEB059336; Thu, 12 Aug 2010 11:00:45 GMT (envelope-from jchandra@svn.freebsd.org) Received: (from jchandra@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o7CB0jOB059331; Thu, 12 Aug 2010 11:00:45 GMT (envelope-from jchandra@svn.freebsd.org) Message-Id: <201008121100.o7CB0jOB059331@svn.freebsd.org> From: "Jayachandran C." Date: Thu, 12 Aug 2010 11:00:45 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r211218 - head/sys/mips/mips X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Aug 2010 11:00:46 -0000 Author: jchandra Date: Thu Aug 12 11:00:45 2010 New Revision: 211218 URL: http://svn.freebsd.org/changeset/base/211218 Log: SMP support in n64. - Enable KX and UX bits on CPU startup for non-boot CPUs - Keep the KX bit when in userspace - XTLB handler needs it to access PCPU data - revert r210638 partly - we don't need to enable KX on kernel entry now Reviewed by: jmallett, imp Modified: head/sys/mips/mips/exception.S head/sys/mips/mips/mpboot.S head/sys/mips/mips/pm_machdep.c head/sys/mips/mips/vm_machdep.c Modified: head/sys/mips/mips/exception.S ============================================================================== --- head/sys/mips/mips/exception.S Thu Aug 12 10:09:28 2010 (r211217) +++ head/sys/mips/mips/exception.S Thu Aug 12 11:00:45 2010 (r211218) @@ -434,12 +434,6 @@ NNON_LEAF(MipsUserGenException, CALLFRAM /* * Save all of the registers except for the kernel temporaries in u.u_pcb. */ - mfc0 k0, MIPS_COP_0_STATUS - HAZARD_DELAY -#ifdef __mips_n64 - ori k1, k0, MIPS_SR_KX - mtc0 k1, MIPS_COP_0_STATUS -#endif GET_CPU_PCPU(k1) PTR_L k1, PC_CURPCB(k1) SAVE_U_PCB_REG(AT, AST, k1) @@ -457,7 +451,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAM SAVE_U_PCB_REG(t2, T2, k1) SAVE_U_PCB_REG(t3, T3, k1) SAVE_U_PCB_REG(ta0, TA0, k1) - move a0, k0 # First arg is the status reg. + mfc0 a0, MIPS_COP_0_STATUS # First arg is the status reg. SAVE_U_PCB_REG(ta1, TA1, k1) SAVE_U_PCB_REG(ta2, TA2, k1) SAVE_U_PCB_REG(ta3, TA3, k1) @@ -656,12 +650,6 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r * Save the relevant user registers into the u.u_pcb struct. * We don't need to save s0 - s8 because the compiler does it for us. */ - mfc0 k0, MIPS_COP_0_STATUS - HAZARD_DELAY -#ifdef __mips_n64 - ori k1, k0, MIPS_SR_KX - mtc0 k1, MIPS_COP_0_STATUS -#endif GET_CPU_PCPU(k1) PTR_L k1, PC_CURPCB(k1) SAVE_U_PCB_REG(AT, AST, k1) @@ -700,7 +688,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r mflo v0 # get lo/hi late to avoid stall mfhi v1 - move a0, k0 + mfc0 a0, MIPS_COP_0_STATUS mfc0 a1, MIPS_COP_0_CAUSE MFC0 a3, MIPS_COP_0_EXC_PC SAVE_U_PCB_REG(v0, MULLO, k1) Modified: head/sys/mips/mips/mpboot.S ============================================================================== --- head/sys/mips/mips/mpboot.S Thu Aug 12 10:09:28 2010 (r211217) +++ head/sys/mips/mips/mpboot.S Thu Aug 12 11:00:45 2010 (r211218) @@ -36,7 +36,8 @@ .set noat .set noreorder -#ifdef CPU_CNMIPS +/* XXX move this to a header file */ +#if defined(CPU_CNMIPS) #define CLEAR_STATUS \ mfc0 a0, MIPS_COP_0_STATUS ;\ li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \ @@ -44,6 +45,10 @@ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER | MIPS_SR_BEV) ; \ and a0, a0, a2 ; \ mtc0 a0, MIPS_COP_0_STATUS +#elif defined(__mips_n64) +#define CLEAR_STATUS \ + li a0, (MIPS_SR_KX | MIPS_SR_UX) ; \ + mtc0 a0, MIPS_COP_0_STATUS #else #define CLEAR_STATUS \ mtc0 zero, MIPS_COP_0_STATUS Modified: head/sys/mips/mips/pm_machdep.c ============================================================================== --- head/sys/mips/mips/pm_machdep.c Thu Aug 12 10:09:28 2010 (r211217) +++ head/sys/mips/mips/pm_machdep.c Thu Aug 12 11:00:45 2010 (r211218) @@ -517,7 +517,7 @@ exec_setregs(struct thread *td, struct i #if defined(__mips_n32) td->td_frame->sr |= MIPS_SR_PX; #elif defined(__mips_n64) - td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX; + td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX; #endif #ifdef CPU_CNMIPS td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS_SR_PX | MIPS_SR_UX | Modified: head/sys/mips/mips/vm_machdep.c ============================================================================== --- head/sys/mips/mips/vm_machdep.c Thu Aug 12 10:09:28 2010 (r211217) +++ head/sys/mips/mips/vm_machdep.c Thu Aug 12 11:00:45 2010 (r211218) @@ -419,7 +419,7 @@ cpu_set_upcall_kse(struct thread *td, vo #if defined(__mips_n32) td->td_frame->sr |= MIPS_SR_PX; #elif defined(__mips_n64) - td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX; + td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX; #endif #ifdef CPU_CNMIPS tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_UX |