Date: Wed, 13 Jun 2001 14:22:15 -0400 (EDT) From: Andrew Gallatin <gallatin@cs.duke.edu> To: mjacob@feral.com Cc: John Baldwin <jhb@FreeBSD.ORG>, freebsd-alpha@FreeBSD.ORG, wilko@FreeBSD.ORG Subject: Re: followup on 8 way SMP pani Message-ID: <15143.44887.290985.930683@grasshopper.cs.duke.edu> In-Reply-To: <Pine.BSF.4.21.0106131101280.40934-100000@beppo.feral.com> References: <XFMail.010613110037.jhb@FreeBSD.org> <Pine.BSF.4.21.0106131101280.40934-100000@beppo.feral.com>
next in thread | previous in thread | raw e-mail | index | archive | help
Matthew Jacob writes:
> > Hang on a second. Clock interrupts are used for _two_ different things
> > here, which is where you are getting confused I think. One is
> > timekeeping, another is to handle things like per-process statclock, etc.
> > All that per-process stuff we do on _all_ cpu's when we get a clock
> > interrupt. Alpha is nice in that it broadcasts clock interrupts for this
> > purpose. On x86, for example, we only have one clock interrupt and we
> > have to IPI all the other CPU's to get this info.
>
> But, in fact, in this case this is *not* a broadcast interrupt. Each TLSB CPU
> board can have up to two CPUs. Each TLSB CPU board has an interval timer and a
> Zilog duart. You use the TLINTRMASK{0,1} registers for each TLSB CPU board to
> control whether one or both CPUs get DUART or Interval Timer or IPI (or any
> other, for that matter) interrupt.
>
The Sable/Lynx family has a similar register (but per-cpu). It has
bits which control if that cpu gets Interval Timer, IPI, etc
interrupts.
Also, from the docs & emperical evidence, it would appear that clock
interrupts arrive at the same frequency, but cpu1 always interrupts
1/4 of a hz after cpu0, cpu2 is 1/2hz behind cpu0, etc.
Drew
To Unsubscribe: send mail to majordomo@FreeBSD.org
with "unsubscribe freebsd-alpha" in the body of the message
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?15143.44887.290985.930683>