From owner-svn-src-head@freebsd.org Wed Aug 12 09:55:52 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id DC99499EE59; Wed, 12 Aug 2015 09:55:52 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id CD5E777; Wed, 12 Aug 2015 09:55:52 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id t7C9tqi6056227; Wed, 12 Aug 2015 09:55:52 GMT (envelope-from kib@FreeBSD.org) Received: (from kib@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id t7C9tqWD056226; Wed, 12 Aug 2015 09:55:52 GMT (envelope-from kib@FreeBSD.org) Message-Id: <201508120955.t7C9tqWD056226@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: kib set sender to kib@FreeBSD.org using -f From: Konstantin Belousov Date: Wed, 12 Aug 2015 09:55:52 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r286659 - head/sys/x86/x86 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Aug 2015 09:55:53 -0000 Author: kib Date: Wed Aug 12 09:55:52 2015 New Revision: 286659 URL: https://svnweb.freebsd.org/changeset/base/286659 Log: In x2APIC mode, IPI generation is atomic because it is performed by single ICR MSR write. This is in contrast with the xAPIC mode, where we must read current ICR value, do bit fiddling and perform two 32-bit register writes. As a consequence, there is no need to disable interrupts around ICR value calculation and write. Note that typical users of ipi_raw() and ipi_vectored() take spinlock, which already disables interrupts. For them, the change removes unneeded CLI and POPFL/Q instructions. Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Modified: head/sys/x86/x86/local_apic.c Modified: head/sys/x86/x86/local_apic.c ============================================================================== --- head/sys/x86/x86/local_apic.c Wed Aug 12 09:46:39 2015 (r286658) +++ head/sys/x86/x86/local_apic.c Wed Aug 12 09:55:52 2015 (r286659) @@ -1657,9 +1657,10 @@ native_lapic_ipi_raw(register_t icrlo, u ("%s: reserved bits set in ICR LO register", __func__)); /* Set destination in ICR HI register if it is being used. */ - saveintr = intr_disable(); - if (!x2apic_mode) + if (!x2apic_mode) { + saveintr = intr_disable(); icr = lapic_read_icr(); + } if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { if (x2apic_mode) { @@ -1682,7 +1683,8 @@ native_lapic_ipi_raw(register_t icrlo, u vlo |= icrlo; } lapic_write_icr(vhi, vlo); - intr_restore(saveintr); + if (!x2apic_mode) + intr_restore(saveintr); } #define BEFORE_SPIN 50000