Date: Wed, 12 Aug 2015 09:55:52 +0000 (UTC) From: Konstantin Belousov <kib@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r286659 - head/sys/x86/x86 Message-ID: <201508120955.t7C9tqWD056226@repo.freebsd.org>
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Author: kib Date: Wed Aug 12 09:55:52 2015 New Revision: 286659 URL: https://svnweb.freebsd.org/changeset/base/286659 Log: In x2APIC mode, IPI generation is atomic because it is performed by single ICR MSR write. This is in contrast with the xAPIC mode, where we must read current ICR value, do bit fiddling and perform two 32-bit register writes. As a consequence, there is no need to disable interrupts around ICR value calculation and write. Note that typical users of ipi_raw() and ipi_vectored() take spinlock, which already disables interrupts. For them, the change removes unneeded CLI and POPFL/Q instructions. Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Modified: head/sys/x86/x86/local_apic.c Modified: head/sys/x86/x86/local_apic.c ============================================================================== --- head/sys/x86/x86/local_apic.c Wed Aug 12 09:46:39 2015 (r286658) +++ head/sys/x86/x86/local_apic.c Wed Aug 12 09:55:52 2015 (r286659) @@ -1657,9 +1657,10 @@ native_lapic_ipi_raw(register_t icrlo, u ("%s: reserved bits set in ICR LO register", __func__)); /* Set destination in ICR HI register if it is being used. */ - saveintr = intr_disable(); - if (!x2apic_mode) + if (!x2apic_mode) { + saveintr = intr_disable(); icr = lapic_read_icr(); + } if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { if (x2apic_mode) { @@ -1682,7 +1683,8 @@ native_lapic_ipi_raw(register_t icrlo, u vlo |= icrlo; } lapic_write_icr(vhi, vlo); - intr_restore(saveintr); + if (!x2apic_mode) + intr_restore(saveintr); } #define BEFORE_SPIN 50000
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