From owner-freebsd-bugs@FreeBSD.ORG Sun Mar 6 10:50:12 2011 Return-Path: Delivered-To: freebsd-bugs@hub.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 4AA5D1065677 for ; Sun, 6 Mar 2011 10:50:12 +0000 (UTC) (envelope-from gnats@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:4f8:fff6::28]) by mx1.freebsd.org (Postfix) with ESMTP id D73268FC12 for ; Sun, 6 Mar 2011 10:50:08 +0000 (UTC) Received: from freefall.freebsd.org (localhost [127.0.0.1]) by freefall.freebsd.org (8.14.4/8.14.4) with ESMTP id p26Ao8qA074808 for ; Sun, 6 Mar 2011 10:50:08 GMT (envelope-from gnats@freefall.freebsd.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.14.4/8.14.4/Submit) id p26Ao8DQ074807; Sun, 6 Mar 2011 10:50:08 GMT (envelope-from gnats) Resent-Date: Sun, 6 Mar 2011 10:50:08 GMT Resent-Message-Id: <201103061050.p26Ao8DQ074807@freefall.freebsd.org> Resent-From: FreeBSD-gnats-submit@FreeBSD.org (GNATS Filer) Resent-To: freebsd-bugs@FreeBSD.org Resent-Reply-To: FreeBSD-gnats-submit@FreeBSD.org, Martin Matuska Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 0B5DD106566C for ; Sun, 6 Mar 2011 10:48:15 +0000 (UTC) (envelope-from mm@mail2.vx.sk) Received: from mail2.vx.sk (mail2.vx.sk [IPv6:2a01:4f8:100:84a3::3]) by mx1.freebsd.org (Postfix) with ESMTP id 484538FC15 for ; Sun, 6 Mar 2011 10:48:13 +0000 (UTC) Received: from neo.vx.sk (localhost [127.0.0.1]) by mail2.vx.sk (Postfix) with ESMTP id 58860F1DEA for ; Sun, 6 Mar 2011 11:48:12 +0100 (CET) Received: from mail2.vx.sk ([127.0.0.1]) by neo.vx.sk (mail.vx.sk [127.0.0.1]) (amavisd-new, port 10024) with LMTP id vU0ij4I571ee for ; Sun, 6 Mar 2011 11:43:09 +0100 (CET) Received: by mail2.vx.sk (Postfix, from userid 1001) id BD757F1DD6; Sun, 6 Mar 2011 11:43:09 +0100 (CET) Message-Id: <20110306104309.BD757F1DD6@mail2.vx.sk> Date: Sun, 6 Mar 2011 11:43:09 +0100 (CET) From: Martin Matuska To: FreeBSD-gnats-submit@FreeBSD.org X-Send-Pr-Version: 3.113 Cc: Subject: gnu/155308: [PATCH] gcc: backport geode and core2 march options X-BeenThere: freebsd-bugs@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: Martin Matuska List-Id: Bug reports List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 06 Mar 2011 10:50:12 -0000 >Number: 155308 >Category: gnu >Synopsis: [PATCH] gcc: backport geode and core2 march options >Confidential: no >Severity: non-critical >Priority: low >Responsible: freebsd-bugs >State: open >Quarter: >Keywords: >Date-Required: >Class: change-request >Submitter-Id: current-users >Arrival-Date: Sun Mar 06 10:50:08 UTC 2011 >Closed-Date: >Last-Modified: >Originator: Martin Matuska >Release: FreeBSD 9-CURRENT amd64 >Organization: >Environment: >Description: Backport CPU types AMD geode and core2 to gcc. These options are supported in all later GCC's, the change is GPLv2-licensed. I recommend backporting these options to contrib/gcc and adding the new flags to share/mk/bsd.cpu.mk The gcc-4.3 branch SVN revisions are 118090, 118973 and 120846, are fully compatible with our code and apply almost completely cleanly (the only reject is one line where bswap32/64 have been added). The SSSE3 instruction set is of course not supported, but this is the same as in gcc-4.3 r118973 (it was added to gcc-4.3 later than core2/geode support). The latest binutils import in base of head supports SSSE3, so the SSSE3 support may be imported at a later point. References: http://gcc.gnu.org/viewcvs?view=revision&revision=118090 http://gcc.gnu.org/viewcvs?view=revision&revision=118973 http://gcc.gnu.org/viewcvs?view=revision&revision=120846 >How-To-Repeat: >Fix: Index: contrib/gcc/doc/invoke.texi =================================================================== --- contrib/gcc/doc/invoke.texi (revision 219330) +++ contrib/gcc/doc/invoke.texi (working copy) @@ -9369,6 +9369,9 @@ @item nocona Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE, SSE2 and SSE3 instruction set support. +@item core2 +Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 +instruction set support. @item k6 AMD K6 CPU with MMX instruction set support. @item k6-2, k6-3 @@ -9396,6 +9399,8 @@ @item c3-2 Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is implemented for this chip.) +@item geode +Embedded AMD CPU with MMX and 3dNOW! instruction set support. @end table While picking a specific @var{cpu-type} will schedule things appropriately Index: contrib/gcc/config.gcc =================================================================== --- contrib/gcc/config.gcc (revision 219330) +++ contrib/gcc/config.gcc (working copy) @@ -1207,14 +1207,14 @@ # FIXME: -m64 for i[34567]86-*-* should be allowed just # like -m32 for x86_64-*-*. case X"${with_cpu}" in - Xgeneric|Xnocona|Xx86-64|Xk8|Xopteron|Xathlon64|Xathlon-fx) + Xgeneric|Xcore2|Xnocona|Xx86-64|Xk8|Xopteron|Xathlon64|Xathlon-fx) ;; X) with_cpu=generic ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic nocona x86-64 k8 opteron athlon64 athlon-fx" 1>&2 + echo "generic core2 nocona x86-64 k8 opteron athlon64 athlon-fx" 1>&2 exit 1 ;; esac @@ -2537,6 +2537,9 @@ nocona-*) with_cpu=nocona ;; + core2-*) + with_cpu=core2 + ;; pentium_m-*) with_cpu=pentium-m ;; @@ -2556,6 +2559,9 @@ nocona-*) with_cpu=nocona ;; + core2-*) + with_cpu=core2 + ;; *) with_cpu=generic ;; @@ -2787,7 +2793,7 @@ esac # OK ;; - "" | k8 | opteron | athlon64 | athlon-fx | nocona | generic) + "" | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | generic) # OK ;; *) Index: contrib/gcc/config/i386/i386.h =================================================================== --- contrib/gcc/config/i386/i386.h (revision 219330) +++ contrib/gcc/config/i386/i386.h (working copy) @@ -130,12 +130,14 @@ #define TARGET_486 (ix86_tune == PROCESSOR_I486) #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) +#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) #define TARGET_K6 (ix86_tune == PROCESSOR_K6) #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) #define TARGET_K8 (ix86_tune == PROCESSOR_K8) #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) +#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) @@ -376,6 +378,10 @@ break; \ } \ } \ + else if (TARGET_GEODE) \ + { \ + builtin_define ("__tune_geode__"); \ + } \ else if (TARGET_K6) \ { \ builtin_define ("__tune_k6__"); \ @@ -397,6 +403,8 @@ builtin_define ("__tune_pentium4__"); \ else if (TARGET_NOCONA) \ builtin_define ("__tune_nocona__"); \ + else if (TARGET_CORE2) \ + builtin_define ("__tune_core2__"); \ \ if (TARGET_MMX) \ builtin_define ("__MMX__"); \ @@ -437,6 +445,11 @@ builtin_define ("__pentiumpro"); \ builtin_define ("__pentiumpro__"); \ } \ + else if (ix86_arch == PROCESSOR_GEODE) \ + { \ + builtin_define ("__geode"); \ + builtin_define ("__geode__"); \ + } \ else if (ix86_arch == PROCESSOR_K6) \ { \ \ @@ -470,6 +483,11 @@ builtin_define ("__nocona"); \ builtin_define ("__nocona__"); \ } \ + else if (ix86_arch == PROCESSOR_CORE2) \ + { \ + builtin_define ("__core2"); \ + builtin_define ("__core2__"); \ + } \ } \ while (0) @@ -481,23 +499,25 @@ #define TARGET_CPU_DEFAULT_pentium2 5 #define TARGET_CPU_DEFAULT_pentium3 6 #define TARGET_CPU_DEFAULT_pentium4 7 -#define TARGET_CPU_DEFAULT_k6 8 -#define TARGET_CPU_DEFAULT_k6_2 9 -#define TARGET_CPU_DEFAULT_k6_3 10 -#define TARGET_CPU_DEFAULT_athlon 11 -#define TARGET_CPU_DEFAULT_athlon_sse 12 -#define TARGET_CPU_DEFAULT_k8 13 -#define TARGET_CPU_DEFAULT_pentium_m 14 -#define TARGET_CPU_DEFAULT_prescott 15 -#define TARGET_CPU_DEFAULT_nocona 16 -#define TARGET_CPU_DEFAULT_generic 17 +#define TARGET_CPU_DEFAULT_geode 8 +#define TARGET_CPU_DEFAULT_k6 9 +#define TARGET_CPU_DEFAULT_k6_2 10 +#define TARGET_CPU_DEFAULT_k6_3 11 +#define TARGET_CPU_DEFAULT_athlon 12 +#define TARGET_CPU_DEFAULT_athlon_sse 13 +#define TARGET_CPU_DEFAULT_k8 14 +#define TARGET_CPU_DEFAULT_pentium_m 15 +#define TARGET_CPU_DEFAULT_prescott 16 +#define TARGET_CPU_DEFAULT_nocona 17 +#define TARGET_CPU_DEFAULT_core2 18 +#define TARGET_CPU_DEFAULT_generic 19 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ "pentiumpro", "pentium2", "pentium3", \ - "pentium4", "k6", "k6-2", "k6-3",\ + "pentium4", "geode", "k6", "k6-2", "k6-3", \ "athlon", "athlon-4", "k8", \ "pentium-m", "prescott", "nocona", \ - "generic"} + "core2", "generic"} #ifndef CC1_SPEC #define CC1_SPEC "%(cc1_cpu) " @@ -2077,11 +2097,13 @@ PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, + PROCESSOR_GEODE, PROCESSOR_K6, PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_K8, PROCESSOR_NOCONA, + PROCESSOR_CORE2, PROCESSOR_GENERIC32, PROCESSOR_GENERIC64, PROCESSOR_max Index: contrib/gcc/config/i386/i386.md =================================================================== --- contrib/gcc/config/i386/i386.md (revision 219330) +++ contrib/gcc/config/i386/i386.md (working copy) @@ -187,7 +187,7 @@ ;; Processor type. This attribute must exactly match the processor_type ;; enumeration in i386.h. -(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona,generic32,generic64" +(define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,nocona,core2,generic32,generic64" (const (symbol_ref "ix86_tune"))) ;; A basic instruction type. Refinements due to arguments to be @@ -473,6 +473,7 @@ (include "ppro.md") (include "k6.md") (include "athlon.md") +(include "geode.md") ;; Operand and operator predicates and constraints Index: contrib/gcc/config/i386/geode.md =================================================================== --- contrib/gcc/config/i386/geode.md (revision 0) +++ contrib/gcc/config/i386/geode.md (revision 0) @@ -0,0 +1,153 @@ +;; Geode Scheduling +;; Copyright (C) 2006 +;; Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to +;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, +;; Boston, MA 02110-1301, USA. +;; +;; The Geode architecture is one insn issue processor. +;; +;; This description is based on data from the following documents: +;; +;; "AMD Geode GX Processor Data Book" +;; Advanced Micro Devices, Inc., Aug 2005. +;; +;; "AMD Geode LX Processor Data Book" +;; Advanced Micro Devices, Inc., Jan 2006. +;; +;; +;; CPU execution units of the Geode: +;; +;; issue describes the issue pipeline. +;; alu describes the Integer unit +;; fpu describes the FP unit +;; +;; The fp unit is out of order execution unit with register renaming. +;; There is also memory management unit and execution pipeline for +;; load/store operations. We ignore it and difference between insns +;; using memory and registers. + +(define_automaton "geode") + +(define_cpu_unit "geode_issue,geode_alu,geode_fpu" "geode") + +(define_insn_reservation "alu" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "alu,alu1,negnot,icmp,lea,test,imov,imovx,icmov,incdec,setcc")) + "geode_issue,geode_alu") + +(define_insn_reservation "shift" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "ishift,ishift1,rotate,rotate1,cld")) + "geode_issue,geode_alu*2") + +(define_insn_reservation "imul" 7 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "imul")) + "geode_issue,geode_alu*7") + +(define_insn_reservation "idiv" 40 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "idiv")) + "geode_issue,geode_alu*40") + +;; The branch unit. +(define_insn_reservation "call" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "call,callv")) + "geode_issue,geode_alu*2") + +(define_insn_reservation "geode_branch" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "ibr")) + "geode_issue,geode_alu") + +(define_insn_reservation "geode_pop_push" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "pop,push")) + "geode_issue,geode_alu") + +(define_insn_reservation "geode_leave" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "leave")) + "geode_issue,geode_alu*2") + +(define_insn_reservation "geode_load_str" 4 + (and (eq_attr "cpu" "geode") + (and (eq_attr "type" "str") + (eq_attr "memory" "load,both"))) + "geode_issue,geode_alu*4") + +(define_insn_reservation "geode_store_str" 2 + (and (eq_attr "cpu" "geode") + (and (eq_attr "type" "str") + (eq_attr "memory" "store"))) + "geode_issue,geode_alu*2") + +;; Be optimistic +(define_insn_reservation "geode_unknown" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "multi,other")) + "geode_issue,geode_alu") + +;; FPU + +(define_insn_reservation "geode_fop" 6 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fop,fcmp")) + "geode_issue,geode_fpu*6") + +(define_insn_reservation "geode_fsimple" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fmov,fcmov,fsgn,fxch")) + "geode_issue,geode_fpu") + +(define_insn_reservation "geode_fist" 4 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fistp,fisttp")) + "geode_issue,geode_fpu*4") + +(define_insn_reservation "geode_fmul" 10 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fmul")) + "geode_issue,geode_fpu*10") + +(define_insn_reservation "geode_fdiv" 47 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fdiv")) + "geode_issue,geode_fpu*47") + +;; We use minimal latency (fsin) here +(define_insn_reservation "geode_fpspc" 54 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fpspc")) + "geode_issue,geode_fpu*54") + +(define_insn_reservation "geode_frndint" 12 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "frndint")) + "geode_issue,geode_fpu*12") + +(define_insn_reservation "geode_mmxmov" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "mmxmov")) + "geode_issue,geode_fpu") + +(define_insn_reservation "geode_mmx" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "mmx,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")) + "geode_issue,geode_fpu*2") Index: contrib/gcc/config/i386/i386.c =================================================================== --- contrib/gcc/config/i386/i386.c (revision 219330) +++ contrib/gcc/config/i386/i386.c (working copy) @@ -336,6 +336,60 @@ }; static const +struct processor_costs geode_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (2), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (7), /* SI */ + COSTS_N_INSNS (7), /* DI */ + COSTS_N_INSNS (7)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (23), /* HI */ + COSTS_N_INSNS (39), /* SI */ + COSTS_N_INSNS (39), /* DI */ + COSTS_N_INSNS (39)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 4, /* MOVE_RATIO */ + 1, /* cost for loading QImode using movzbl */ + {1, 1, 1}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {1, 1, 1}, /* cost of storing integer registers */ + 1, /* cost of reg,reg fld/fst */ + {1, 1, 1}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {4, 6, 6}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + + 1, /* cost of moving MMX register */ + {1, 1}, /* cost of loading MMX registers + in SImode and DImode */ + {1, 1}, /* cost of storing MMX registers + in SImode and DImode */ + 1, /* cost of moving SSE register */ + {1, 1, 1}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {1, 1, 1}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 1, /* MMX or SSE register to integer */ + 32, /* size of prefetch block */ + 1, /* number of parallel prefetches */ + 1, /* Branch cost */ + COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (11), /* cost of FMUL instruction. */ + COSTS_N_INSNS (47), /* cost of FDIV instruction. */ + COSTS_N_INSNS (1), /* cost of FABS instruction. */ + COSTS_N_INSNS (1), /* cost of FCHS instruction. */ + COSTS_N_INSNS (54), /* cost of FSQRT instruction. */ +}; + +static const struct processor_costs k6_cost = { COSTS_N_INSNS (1), /* cost of an add instruction */ COSTS_N_INSNS (2), /* cost of a lea instruction */ @@ -600,6 +654,58 @@ COSTS_N_INSNS (44), /* cost of FSQRT instruction. */ }; +static const +struct processor_costs core2_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (3), /* HI */ + COSTS_N_INSNS (3), /* SI */ + COSTS_N_INSNS (3), /* DI */ + COSTS_N_INSNS (3)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (22), /* HI */ + COSTS_N_INSNS (22), /* SI */ + COSTS_N_INSNS (22), /* DI */ + COSTS_N_INSNS (22)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 16, /* MOVE_RATIO */ + 2, /* cost for loading QImode using movzbl */ + {6, 6, 6}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {4, 4, 4}, /* cost of storing integer registers */ + 2, /* cost of reg,reg fld/fst */ + {6, 6, 6}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {4, 4, 4}, /* cost of loading integer registers */ + 2, /* cost of moving MMX register */ + {6, 6}, /* cost of loading MMX registers + in SImode and DImode */ + {4, 4}, /* cost of storing MMX registers + in SImode and DImode */ + 2, /* cost of moving SSE register */ + {6, 6, 6}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {4, 4, 4}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 2, /* MMX or SSE register to integer */ + 128, /* size of prefetch block */ + 8, /* number of parallel prefetches */ + 3, /* Branch cost */ + COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (5), /* cost of FMUL instruction. */ + COSTS_N_INSNS (32), /* cost of FDIV instruction. */ + COSTS_N_INSNS (1), /* cost of FABS instruction. */ + COSTS_N_INSNS (1), /* cost of FCHS instruction. */ + COSTS_N_INSNS (58), /* cost of FSQRT instruction. */ +}; + /* Generic64 should produce code tuned for Nocona and K8. */ static const struct processor_costs generic64_cost = { @@ -721,38 +827,41 @@ #define m_486 (1<Release-Note: >Audit-Trail: >Unformatted: