From owner-freebsd-hackers@FreeBSD.ORG Thu Jul 29 21:41:23 2010 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 7A391106567B for ; Thu, 29 Jul 2010 21:41:23 +0000 (UTC) (envelope-from pebu3op@googlemail.com) Received: from mail.net.t-labs.tu-berlin.de (mail.net.t-labs.tu-berlin.de [130.149.220.252]) by mx1.freebsd.org (Postfix) with ESMTP id 0F9AF8FC0C for ; Thu, 29 Jul 2010 21:41:22 +0000 (UTC) Received: from raven.net.t-labs.tu-berlin.de (raven.net.t-labs.tu-berlin.de [130.149.220.18]) by mail.net.t-labs.tu-berlin.de (Postfix) with ESMTP id 0DEF5700D29E; Thu, 29 Jul 2010 23:41:22 +0200 (CEST) From: Alexander Fiveg Organization: Google To: Andriy Gapon Date: Thu, 29 Jul 2010 23:41:20 +0200 User-Agent: KMail/1.9.10 References: <382607918.1356296.1280433776963.JavaMail.root@vms170009.mailsrvcs.net> <4C51E198.8060800@icyb.net.ua> In-Reply-To: <4C51E198.8060800@icyb.net.ua> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Message-Id: <201007292341.21123.pebu3op@googlemail.com> Cc: freebsd-hackers@freebsd.org, Sergey Babkin Subject: Re: coherence-problem on the mapped memory buffer X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: pebu3op@googlemail.com List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Jul 2010 21:41:23 -0000 On Thursday 29 July 2010 22:16:24 Andriy Gapon wrote: > on 29/07/2010 23:02 Sergey Babkin said the following: > > Jul 29, 2010 12:58:07 PM, avg@icyb.net.ua wrote: > >> on 29/07/2010 19:13 Andriy Gapon said the following: > >>> on 29/07/2010 17:13 Alexander Fiveg said the following: > >> > >> In fact I have a suspicion that the problem might have to do with > >> multiple mappings of the shared pages, but far from sure... > >> Take a look at Intel=C2=AE 64 and IA-32 Architectures Software Develop= er=E2=80=99s > >> Manual Volume 3A - System Programming Guide, Part 1; Chapter 11.12.4 > >> Programming the PAT; starting at the following words: > >> =C2=ABThe PAT allows any memory type to be specified in the page table= s, and > >> therefore it is possible to have a single physical page mapped to two = or > >> more different linear addresses, each with different memory types. Int= el > >> does not support this practice...=C2=BB > > > > My guess would be that the memory type is not marked as DMA-capable. > > AFAIK the Intel CPUs do the hardware snooping on the physical addresses, > > so they have no coherency issues benween themselves. However if a DMA > > writer changes the memory, this I think does not get normally propagated > > to the front-side bus, and the CPUs would not see it. You may need to > > either explicitly flush the CPU cache before accessing these pages or > > mark them as non-cacheable. > > My guess was approximately the same - if one mapping is done in kernel for > DMA purposes, then the memory type is, most likely, set to uncached. But > the userland mapping of the same pages most likely marks the same pages > (via different virtual addresses) as cached. Depending on the hardware a= nd > on what mappings were used on a particular CPU (core) to access that > memory, there could be differences in interaction with DMA. Thanks a lot for your answers. But i am afraid i do not have enough=20 experience to solve these tasks. Could you please provide me with helpful=20 information how to:=20 =2D get access to the pages associated with a certain memory-buffer ?=20 I mean, I want to get the structures, that describe the page properties I=20 should change (for instance, in order to make the page non-cacheable). if you are aware of any good papers or examples in the system code, where=20 these topics are covered, I would appreciate it if you gave me the=20 references.=20 Alex