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Subject: [Bug 199174] em tx and rx hang
Date: Thu, 09 Apr 2015 00:12:36 +0000
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=199174

--- Comment #5 from david.keller@litchis.fr ---
Let's keep up with the digging.

When hung, the 82574 generates link interrupts at a rate of ~1/s.

The first ICR read value by the link interrupt routine is 0x800000c5
<INT_ASSERTED,RXTO,RXO,LSC,TXDW>.

Then *every* ICR read value is 0x40 <RXO>.

TXDW:
Transmit Descriptor Written Back
Set when hardware processes a descriptor with RS set. If using
delayed interrupts (IDE set), the interrupt is delayed until after one of
the delayed-timers (TIDV or TADV) expires.

LSC:
Link Status Change
This bit is set whenever the link status changes (either from up to
down, or from down to up). This bit is affected by the link indication
from the PHY.

RXO:
Receiver Overrun
Set on receive data FIFO overrun. Could be caused either because
there are no available buffers or because PCIe receive bandwidth is
inadequate

RXT0:
Receiver Timer Interrupt
Set when the timer expires.

INT_ASSRTED:
Interrupt Asserted
This bit is set when the LAN port has a pending interrupt. If the
interrupt is enabled in the PCI configuration space, an interrupt is
asserted.

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