Date: Mon, 23 Jun 1997 13:39:05 -0600 From: Steve Passe <smp@csn.net> To: Lars Fredriksen <lars@fredriks-1.pr.mcs.net> Cc: smp@freebsd.org Subject: Re: SMP kernel hung...more info Message-ID: <199706231939.NAA07051@Ilsa.StevesCafe.com> In-Reply-To: Your message of "Mon, 23 Jun 1997 13:39:31 CDT." <199706231839.NAA00727@fredriks-1.pr.mcs.net>
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Hi, Lars has been struggling with his SMP system and just sent me his mptable output. It has something bogus in it, am wondering if anyone else with a supermicro has a similar table. specifically: I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID INT# INT active-lo level 0 19:A 2 16 INT active-lo level 0 18:A 2 16 INT active-lo level 0 17:A 2 16 INT active-lo level 0 19:A 2 17 INT active-lo level 0 18:A 2 17 INT active-lo level 0 17:A 2 17 INT active-lo level 0 19:A 2 18 INT active-lo level 0 18:A 2 18 INT active-lo level 0 17:A 2 18 INT active-lo level 0 20:A 2 19 note that 19:A is declared to be attached to apic#2, pins 16, 17 and 18. similarily, 18:A is attached to pins 16,17,18. similarily, 17:A is attached to pins 16,17,18. This is totally BOGUS. more than one slot can be on an APIC pin (shared INTs) but each slot should NOT be attached to more than one APIC pin! if this were possible you would trigger three different INT vectors each time a device generated an INT. does anyone have any theories to explain this? does anyone have an mptable with similar entries, ie a slot that is claimed to be attached to more than one APIC pin? --- Lars, the current code just isn't going to work with this mptable. I suggest you don't waste further time trying. We need to talk to someone at supermicro tech support about this to find out whats up. do you have any contacts there? -- Steve Passe | powered by smp@csn.net | Symmetric MultiProcessor FreeBSD
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