Date: Mon, 27 Oct 1997 15:04:41 -0500 From: Jerry Hicks <wghhicks@ix.netcom.com> To: "Jamil J. Weatherbee" <jamil@trojanhorse.ml.org> Cc: freebsd-hackers@FreeBSD.ORG Subject: Re: Parity Ram Message-ID: <3454F3D9.88D5318C@ix.netcom.com> References: <Pine.BSF.3.96.971025115335.173A-100000@trojanhorse.ml.org>
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Jamil J. Weatherbee wrote: > > Can someone fill me in on when you would want to use parity ram as opposed > to non-parity ram these days? If there was some anomaly in memory how > would freebsd handle it (is there a trap for parity error?) Here's the best I've been able to find @ www.dejanews.com: > From: tatosian@eng.pko.xxx.com > Re: Parity vs. ECC on HX chipset > Date: 1997/10/03 > > First, of the 72-pin SIMM types, there are 32-bit SIMMs, 36-bit "True Parity" > SIMMs, 32-bit "Fake Parity" SIMMs, and 36-bit "ECC" SIMMs. > > o 32-bit SIMMs: can't do (or even fake) parity or ECC operation. Can be > constructed using anything from a bagfull of "X1" parts through a pair of > "X16" DRAMs. > > o "True Parity" SIMMs: 32 bits of data, plus 4 parity bits. Each of the 4 CAS > lines on the SIMM *must* control 8 data bits (a byte) plus a parity bit in > order to operate correctly under parity mode, which requires "byte write" > support. > > While the data bits are now most commonly constructed using DRAMs that are 4, > 8, or 16 bits "wide", the parity bits must be constructed using either (4) > "X1" DRAMs, or a single "quad CAS" DRAM that is 4-bits wide. As the latter > parts are somewhat rare (not every memory manufacturer produces them) and > somewhat more costly than a standard "X4" part, not to mention that the 4 "X1" > implementation uses older, less dense generation parts, the 4 "X1" > implementation is the more common. > > This type of SIMM can obviously be used in parity mode, and can also be used > in ECC mode *if* the chipset activates all (4) CAS signals on every operation > to the SIMM (and if the motherboard routes those same CAS signals to the > correct SIMM pins). > > The name "True Parity" wouldn't be necessary, if it wasn't for the nefarious > > o "Fake Parity" SIMMs: provide only a 32-bit wide storage path to the DRAMs, > but include a (4) byte-parity generator that coughs up 4 parity bits from the > 32 databits when the SIMM is read by the system. > > Simply a forgettable piece of crap that unfortunately cost many people a > premium because they weren't aware of what they were getting. > > And finally, > > o ECC SIMM: This SIMM provides a unified 36-bit wide datapath that operates > with (logically) a single RAS signal and a single CAS signal. Ie: this SIMM > does *not* support byte-write operations, and therefore cannot be used on a > system running parity mode. While this SIMM can be constructed using any mix > of "X1" through "X32" parts, it is more commonly built using (9) "X4" parts. > > The ECC SIMM can be operated in ECC mode (obviously), and can also be operated > in non-ECC/non-parity mode - but only if the chipset won't attempt to perform > byte-write operations. Ie: the chipset must use READ-MODIFY-WRITE operations > (similar to those used in ECC mode) if anything less than the full longword > (32 bits) of data are to be changed. > > Hopefully the above illustrates the significant differences between two > different SIMMs that happen to provide 36 bit datapaths... > This thread also discussed that the configuration registers must be properly set up by BIOS to have ECC function properly on an HX motherboard. There was mention of some buggy BIOS's floating around which don't properly set the configuration registers although the screen prompt indicates that ECC is selected. Specific versions weren't indicated. HTH, Jerry Hicks jerry_hicks@bigfoot.com
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