From owner-svn-src-projects@FreeBSD.ORG Thu Feb 20 23:17:46 2014 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 91BA7C83; Thu, 20 Feb 2014 23:17:46 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 7EDFD1C59; Thu, 20 Feb 2014 23:17:46 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s1KNHk5q007831; Thu, 20 Feb 2014 23:17:46 GMT (envelope-from andrew@svn.freebsd.org) Received: (from andrew@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s1KNHkDc007830; Thu, 20 Feb 2014 23:17:46 GMT (envelope-from andrew@svn.freebsd.org) Message-Id: <201402202317.s1KNHkDc007830@svn.freebsd.org> From: Andrew Turner Date: Thu, 20 Feb 2014 23:17:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r262271 - projects/arm64/sys/arm64/include X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Feb 2014 23:17:46 -0000 Author: andrew Date: Thu Feb 20 23:17:46 2014 New Revision: 262271 URL: http://svnweb.freebsd.org/changeset/base/262271 Log: Add more ARM registers Modified: projects/arm64/sys/arm64/include/armreg.h Modified: projects/arm64/sys/arm64/include/armreg.h ============================================================================== --- projects/arm64/sys/arm64/include/armreg.h Thu Feb 20 23:17:24 2014 (r262270) +++ projects/arm64/sys/arm64/include/armreg.h Thu Feb 20 23:17:46 2014 (r262271) @@ -29,6 +29,10 @@ #ifndef _MACHINE_ARMREG_H_ #define _MACHINE_ARMREG_H_ +/* Memory Attribute Indirection register */ +/* TODO: Should this be in a pte header? */ +#define MAIR(attr, idx) ((attr) << ((idx) * 8)) + /* * The various *PSR registers, e.g. cpsr or cpsr. * @@ -81,4 +85,24 @@ #define SCTLR_EE 0x02000000 #define SCTLR_UCI 0x04000000 +/* Translation Control Register */ +#define TCR_ASID_16 (1 << 36) + +#define TCR_IPS_SHIFT 32 +#define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT) +#define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT) +#define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT) +#define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT) +#define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT) +#define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT) + +#define TCR_TG1_SHIFT 30 +#define TCR_TG1_16K (1 << TCR_TG1_SHIFT) +#define TCR_TG1_4K (2 << TCR_TG1_SHIFT) +#define TCR_TG1_64K (3 << TCR_TG1_SHIFT) + +#define TCR_T1SZ_SHIFT 16 +#define TCR_T0SZ_SHIFT 0 +#define TCR_TxSZ(x) (((x) << TCR_T1SZ_SHIFT) | ((x) << TCR_T0SZ_SHIFT)) + #endif