From owner-dev-commits-src-main@freebsd.org Thu Mar 4 16:55:07 2021 Return-Path: Delivered-To: dev-commits-src-main@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 4EFB2551C4D; Thu, 4 Mar 2021 16:55:07 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Drxn71qdTz4Y64; Thu, 4 Mar 2021 16:55:07 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 31B9620BBD; Thu, 4 Mar 2021 16:55:07 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 124Gt7jx090376; Thu, 4 Mar 2021 16:55:07 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 124Gt763090375; Thu, 4 Mar 2021 16:55:07 GMT (envelope-from git) Date: Thu, 4 Mar 2021 16:55:07 GMT Message-Id: <202103041655.124Gt763090375@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Michal Meloun Subject: git: a5dce53b75d8 - main - mvebu_gpio: Multiple fixes. MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mmel X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: a5dce53b75d8750ba95623ad2dbffac4acfd3545 Auto-Submitted: auto-generated X-BeenThere: dev-commits-src-main@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Commit messages for the main branch of the src repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Mar 2021 16:55:07 -0000 The branch main has been updated by mmel: URL: https://cgit.FreeBSD.org/src/commit/?id=a5dce53b75d8750ba95623ad2dbffac4acfd3545 commit a5dce53b75d8750ba95623ad2dbffac4acfd3545 Author: Michal Meloun AuthorDate: 2021-03-03 17:28:45 +0000 Commit: Michal Meloun CommitDate: 2021-03-04 16:54:40 +0000 mvebu_gpio: Multiple fixes. - gpio register access primitives - locking in interrupt path - cleanup In cooperation with: mw Reviewed by: mw (initial version) MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D29044 Differential Revision: https://reviews.freebsd.org/D28911 --- sys/arm/mv/mvebu_gpio.c | 60 ++++++++++++++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 23 deletions(-) diff --git a/sys/arm/mv/mvebu_gpio.c b/sys/arm/mv/mvebu_gpio.c index f0471b8d019c..c38fbceebf24 100644 --- a/sys/arm/mv/mvebu_gpio.c +++ b/sys/arm/mv/mvebu_gpio.c @@ -83,9 +83,6 @@ __FBSDID("$FreeBSD$"); #define MV_GPIO_MAX_NIRQS 4 #define MV_GPIO_MAX_NPINS 32 -#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) -#define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val)) - struct mvebu_gpio_irqsrc { struct intr_irqsrc isrc; u_int irq; @@ -127,14 +124,11 @@ static inline void gpio_write(struct mvebu_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin, uint32_t val) { - uint32_t tmp; int bit; bit = GPIO_BIT(pin->gp_pin); - tmp = 0x100 << bit; /* mask */ - tmp |= (val & 1) << bit; /* value */ SYSCON_WRITE_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg, - tmp); + (val & 1) << bit); } static inline uint32_t @@ -146,9 +140,21 @@ gpio_read(struct mvebu_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin) bit = GPIO_BIT(pin->gp_pin); val = SYSCON_READ_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg); + return (val >> bit) & 1; } +static inline void +gpio_modify(struct mvebu_gpio_softc *sc, bus_size_t reg, + struct gpio_pin *pin, uint32_t val) +{ + int bit; + + bit = GPIO_BIT(pin->gp_pin); + SYSCON_MODIFY_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg, + 1 << bit, (val & 1) << bit); +} + static void mvebu_gpio_pin_configure(struct mvebu_gpio_softc *sc, struct gpio_pin *pin, unsigned int flags) @@ -305,15 +311,14 @@ mvebu_gpio_pin_toggle(device_t dev, uint32_t pin) */ static inline void intr_modify(struct mvebu_gpio_softc *sc, bus_addr_t reg, - struct mvebu_gpio_irqsrc *mgi, uint32_t val, uint32_t mask) + struct mvebu_gpio_irqsrc *mgi, uint32_t val) { int bit; bit = GPIO_BIT(mgi->irq); - GPIO_LOCK(sc); - val = SYSCON_MODIFY_4(sc->syscon, - sc->offset + GPIO_REGNUM(mgi->irq) + reg, val, mask); - GPIO_UNLOCK(sc); + SYSCON_MODIFY_4(sc->syscon, + sc->offset + GPIO_REGNUM(mgi->irq) + reg, 1 << bit, + (val & 1) << bit); } static inline void @@ -322,18 +327,23 @@ mvebu_gpio_isrc_mask(struct mvebu_gpio_softc *sc, { if (mgi->is_level) - intr_modify(sc, GPIO_INT_LEVEL_MASK, mgi, val, 1); + intr_modify(sc, GPIO_INT_LEVEL_MASK, mgi, val); else - intr_modify(sc, GPIO_INT_MASK, mgi, val, 1); + intr_modify(sc, GPIO_INT_MASK, mgi, val); } static inline void mvebu_gpio_isrc_eoi(struct mvebu_gpio_softc *sc, struct mvebu_gpio_irqsrc *mgi) { + int bit; - if (!mgi->is_level) - intr_modify(sc, GPIO_INT_CAUSE, mgi, 0, 1); + if (!mgi->is_level) { + bit = GPIO_BIT(mgi->irq); + SYSCON_WRITE_4(sc->syscon, + sc->offset + GPIO_REGNUM(mgi->irq) + GPIO_INT_CAUSE, + ~(1 << bit)); + } } static int @@ -596,8 +606,11 @@ mvebu_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, mgi->is_level = level; mgi->is_inverted = inverted; - intr_modify(sc, GPIO_DATA_IN_POL, mgi, inverted ? 1 : 0, 1); + + GPIO_LOCK(sc); + intr_modify(sc, GPIO_DATA_IN_POL, mgi, inverted ? 1 : 0); mvebu_gpio_pic_enable_intr(dev, isrc); + GPIO_UNLOCK(sc); return (0); } @@ -641,12 +654,13 @@ mvebu_gpio_intr(void *arg) lvl &= gpio_read(sc, GPIO_INT_LEVEL_MASK, &sc->gpio_pins[i]); edge = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[i]); edge &= gpio_read(sc, GPIO_INT_LEVEL_MASK, &sc->gpio_pins[i]); - if (edge == 0 || lvl == 0) + if (edge == 0 && lvl == 0) continue; mgi = &sc->isrcs[i]; if (!mgi->is_level) mvebu_gpio_isrc_eoi(sc, mgi); + if (intr_isrc_dispatch(&mgi->isrc, tf) != 0) { mvebu_gpio_isrc_mask(sc, mgi, 0); if (mgi->is_level) @@ -776,11 +790,11 @@ mvebu_gpio_attach(device_t dev) snprintf(pin->gp_name, GPIOMAXNAME, "gpio%d", i); /* Init HW */ - gpio_write(sc, GPIO_INT_MASK, pin, 0); - gpio_write(sc, GPIO_INT_LEVEL_MASK, pin, 0); - gpio_write(sc, GPIO_INT_CAUSE, pin, 0); - gpio_write(sc, GPIO_DATA_IN_POL, pin, 1); - gpio_write(sc, GPIO_BLINK_ENA, pin, 0); + gpio_modify(sc, GPIO_INT_MASK, pin, 0); + gpio_modify(sc, GPIO_INT_LEVEL_MASK, pin, 0); + gpio_modify(sc, GPIO_INT_CAUSE, pin, 0); + gpio_modify(sc, GPIO_DATA_IN_POL, pin, 0); + gpio_modify(sc, GPIO_BLINK_ENA, pin, 0); } if (sc->irq_res[0] != NULL) {