From owner-svn-src-all@freebsd.org Tue Aug 21 17:13:53 2018 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id F133E107995E; Tue, 21 Aug 2018 17:13:52 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 965858D3C3; Tue, 21 Aug 2018 17:13:52 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 7215D26EE8; Tue, 21 Aug 2018 17:13:52 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w7LHDqkx049297; Tue, 21 Aug 2018 17:13:52 GMT (envelope-from jhb@FreeBSD.org) Received: (from jhb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w7LHDqut049295; Tue, 21 Aug 2018 17:13:52 GMT (envelope-from jhb@FreeBSD.org) Message-Id: <201808211713.w7LHDqut049295@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhb set sender to jhb@FreeBSD.org using -f From: John Baldwin Date: Tue, 21 Aug 2018 17:13:52 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r338148 - head/sys/x86/isa X-SVN-Group: head X-SVN-Commit-Author: jhb X-SVN-Commit-Paths: head/sys/x86/isa X-SVN-Commit-Revision: 338148 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Aug 2018 17:13:53 -0000 Author: jhb Date: Tue Aug 21 17:13:51 2018 New Revision: 338148 URL: https://svnweb.freebsd.org/changeset/base/338148 Log: Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an invididual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Reviewed by: kib, imp MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16827 Modified: head/sys/x86/isa/atpic.c head/sys/x86/isa/icu.h Modified: head/sys/x86/isa/atpic.c ============================================================================== --- head/sys/x86/isa/atpic.c Tue Aug 21 17:07:52 2018 (r338147) +++ head/sys/x86/isa/atpic.c Tue Aug 21 17:13:51 2018 (r338148) @@ -67,12 +67,12 @@ __FBSDID("$FreeBSD$"); #define MASTER 0 #define SLAVE 1 +#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq)) + #define NUM_ISA_IRQS 16 static void atpic_init(void *dummy); -unsigned int imen; /* XXX */ - inthand_t IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2), IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5), @@ -93,12 +93,24 @@ inthand_t #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq) -#define ATPIC(io, base, eoi, imenptr) \ - { { atpic_enable_source, atpic_disable_source, (eoi), \ - atpic_enable_intr, atpic_disable_intr, atpic_vector, \ - atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\ - atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \ - (imenptr) } +#define ATPIC(io, base, eoi) { \ + .at_pic = { \ + .pic_enable_source = atpic_enable_source, \ + .pic_disable_source = atpic_disable_source, \ + .pic_eoi_source = (eoi), \ + .pic_enable_intr = atpic_enable_intr, \ + .pic_disable_intr = atpic_disable_intr, \ + .pic_vector = atpic_vector, \ + .pic_source_pending = atpic_source_pending, \ + .pic_resume = atpic_resume, \ + .pic_config_intr = atpic_config_intr, \ + .pic_assign_cpu = atpic_assign_cpu \ + }, \ + .at_ioaddr = (io), \ + .at_irqbase = (base), \ + .at_intbase = IDT_IO_INTS + (base), \ + .at_imen = 0xff, \ + } #define INTSRC(irq) \ { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \ @@ -109,7 +121,7 @@ struct atpic { int at_ioaddr; int at_irqbase; uint8_t at_intbase; - uint8_t *at_imen; + uint8_t at_imen; }; struct atpic_intsrc { @@ -136,8 +148,8 @@ static int atpic_assign_cpu(struct intsrc *isrc, u_int static void i8259_init(struct atpic *pic, int slave); static struct atpic atpics[] = { - ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen), - ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1) + ATPIC(IO_ICU1, 0, atpic_eoi_master), + ATPIC(IO_ICU2, 8, atpic_eoi_slave) }; static struct atpic_intsrc atintrs[] = { @@ -197,9 +209,9 @@ atpic_enable_source(struct intsrc *isrc) struct atpic *ap = (struct atpic *)isrc->is_pic; spinlock_enter(); - if (*ap->at_imen & IMEN_MASK(ai)) { - *ap->at_imen &= ~IMEN_MASK(ai); - outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen); + if (ap->at_imen & IMEN_MASK(ai)) { + ap->at_imen &= ~IMEN_MASK(ai); + outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen); } spinlock_exit(); } @@ -212,8 +224,8 @@ atpic_disable_source(struct intsrc *isrc, int eoi) spinlock_enter(); if (ai->at_trigger != INTR_TRIGGER_EDGE) { - *ap->at_imen |= IMEN_MASK(ai); - outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen); + ap->at_imen |= IMEN_MASK(ai); + outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen); } /* @@ -387,7 +399,7 @@ i8259_init(struct atpic *pic, int slave) outb(imr_addr, MASTER_MODE); /* Set interrupt enable mask. */ - outb(imr_addr, *pic->at_imen); + outb(imr_addr, pic->at_imen); /* Reset is finished, default to IRR on read. */ outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR); @@ -406,7 +418,6 @@ atpic_startup(void) int i; /* Start off with all interrupts disabled. */ - imen = 0xffff; i8259_init(&atpics[MASTER], 0); i8259_init(&atpics[SLAVE], 1); atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]); Modified: head/sys/x86/isa/icu.h ============================================================================== --- head/sys/x86/isa/icu.h Tue Aug 21 17:07:52 2018 (r338147) +++ head/sys/x86/isa/icu.h Tue Aug 21 17:13:51 2018 (r338148) @@ -70,7 +70,6 @@ #endif #define IRQ_MASK(irq) (1 << (irq)) -#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq)) void atpic_handle_intr(u_int vector, struct trapframe *frame); void atpic_startup(void);