From owner-cvs-all@FreeBSD.ORG Thu Dec 29 03:48:59 2005 Return-Path: X-Original-To: cvs-all@FreeBSD.org Delivered-To: cvs-all@FreeBSD.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 8152C16A41F; Thu, 29 Dec 2005 03:48:59 +0000 (GMT) (envelope-from edwin@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 04E1C43D58; Thu, 29 Dec 2005 03:48:59 +0000 (GMT) (envelope-from edwin@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.1/8.13.1) with ESMTP id jBT3mwei098858; Thu, 29 Dec 2005 03:48:58 GMT (envelope-from edwin@repoman.freebsd.org) Received: (from edwin@localhost) by repoman.freebsd.org (8.13.1/8.13.1/Submit) id jBT3mwZV098857; Thu, 29 Dec 2005 03:48:58 GMT (envelope-from edwin) Message-Id: <200512290348.jBT3mwZV098857@repoman.freebsd.org> From: Edwin Groothuis Date: Thu, 29 Dec 2005 03:48:58 +0000 (UTC) To: ports-committers@FreeBSD.org, cvs-ports@FreeBSD.org, cvs-all@FreeBSD.org X-FreeBSD-CVS-Branch: HEAD Cc: Subject: cvs commit: ports/cad Makefile ports/cad/gplcver Makefile distinfo pkg-descr X-BeenThere: cvs-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the entire tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Dec 2005 03:48:59 -0000 edwin 2005-12-29 03:48:58 UTC FreeBSD ports repository Modified files: cad Makefile Added files: cad/gplcver Makefile distinfo pkg-descr Log: [NEW PORT] cad/gplcver: A Verilog HDL simulator GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog. WWW: http://www.pragmatic-c.com/gpl-cver/ PR: ports/80968 Submitted by: Ying-Chieh Liao Revision Changes Path 1.80 +1 -0 ports/cad/Makefile 1.1 +28 -0 ports/cad/gplcver/Makefile (new) 1.1 +3 -0 ports/cad/gplcver/distinfo (new) 1.1 +18 -0 ports/cad/gplcver/pkg-descr (new)