From owner-p4-projects@FreeBSD.ORG Sun Nov 2 01:43:11 2003 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 43EE716A4D0; Sun, 2 Nov 2003 01:43:11 -0800 (PST) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 06B0A16A4CE for ; Sun, 2 Nov 2003 01:43:11 -0800 (PST) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 6CB0543F93 for ; Sun, 2 Nov 2003 01:43:10 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.9/8.12.9) with ESMTP id hA29hAXJ061098 for ; Sun, 2 Nov 2003 01:43:10 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.9/8.12.9/Submit) id hA29h9Ut061095 for perforce@freebsd.org; Sun, 2 Nov 2003 01:43:09 -0800 (PST) (envelope-from jmallett@freebsd.org) Date: Sun, 2 Nov 2003 01:43:09 -0800 (PST) Message-Id: <200311020943.hA29h9Ut061095@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to jmallett@freebsd.org using -f From: Juli Mallett To: Perforce Change Reviews Subject: PERFORCE change 41105 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 02 Nov 2003 09:43:11 -0000 http://perforce.freebsd.org/chv.cgi?CH=41105 Change 41105 by jmallett@jmallett_dalek on 2003/11/02 01:42:33 Remove TLBUpdate from NetBSD. Affected files ... .. //depot/projects/mips/sys/mips/include/locore.h#10 edit .. //depot/projects/mips/sys/mips/mips/mips_subr.S#15 edit Differences ... ==== //depot/projects/mips/sys/mips/include/locore.h#10 (text+ko) ==== @@ -34,7 +34,6 @@ void mips64_TBIA(int); void mips64_TBIAP(int); void mips64_TBIS(vm_paddr_t); -int mips64_TLBUpdate(u_int, u_int); void mips64_TLBRead(int, struct tlb *); void mips64_wbflush(void); @@ -46,7 +45,6 @@ #define MIPS_TBIA() mips64_TBIA(mips_num_tlb_entries) #define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries) #define MIPS_TBIS mips64_TBIS -#define MachTLBUpdate mips64_TLBUpdate /* * CPU identification, from PRID register. ==== //depot/projects/mips/sys/mips/mips/mips_subr.S#15 (text+ko) ==== @@ -178,129 +178,6 @@ /*-------------------------------------------------------------------------- * - * mipsN_TLBUpdate -- - * - * Update the TLB if highreg is found; otherwise, enter the data. - * - * mips3_TLBUpdate(virpageadr, lowregx) - * unsigned virpageadr, lowregx; - * - * Results: - * < 0 if loaded >= 0 if updated. - * - * Side effects: - * None. - * - *-------------------------------------------------------------------------- - */ -LEAF(MIPSX(TLBUpdate)) - mfc0 v1, MIPS_COP_0_STATUS # Save the status register. - mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts - COP0_SYNC - and t1, a0, PG_ODDPG # t1 = Even/Odd flag - li v0, (PG_HVPN | PG_ASID) - and a0, a0, v0 - _MFC0 t0, MIPS_COP_0_TLB_HI # Save current PID - _MTC0 a0, MIPS_COP_0_TLB_HI # Init high reg - COP0_SYNC - and a2, a1, PG_G # Copy global bit - nop - nop - tlbp # Probe for the entry. - COP0_SYNC - _SLL a1, a1, WIRED_SHIFT # Clear top 34 bits of EntryLo - _SRL a1, a1, WIRED_SHIFT - bne t1, zero, 2f # Decide even odd - mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got -/* EVEN */ - nop - bltz v0, 1f # index < 0 => !found - nop - nop # required for QED5230 - - tlbr # update, read entry first - COP0_SYNC - nop - nop - nop - _MTC0 a1, MIPS_COP_0_TLB_LO0 # init low reg0. - COP0_SYNC - nop - nop # required for QED5230 - tlbwi # update slot found - COP0_SYNC - nop # required for QED5230 - nop # required for QED5230 - b 4f - nop -1: - mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask. - COP0_SYNC - _MTC0 a0, MIPS_COP_0_TLB_HI # init high reg. - COP0_SYNC - _MTC0 a1, MIPS_COP_0_TLB_LO0 # init low reg0. - COP0_SYNC - _MTC0 a2, MIPS_COP_0_TLB_LO1 # init low reg1. - COP0_SYNC - nop - nop # required for QED5230 - tlbwr # enter into a random slot - COP0_SYNC - nop # required for QED5230 - nop # required for QED5230 - b 4f - nop -/* ODD */ -2: - nop - bltz v0, 3f # index < 0 => !found - nop - nop # required for QED5230 - - tlbr # read the entry first - COP0_SYNC - nop - nop - nop - _MTC0 a1, MIPS_COP_0_TLB_LO1 # init low reg1. - COP0_SYNC - nop - nop # required for QED5230 - tlbwi # update slot found - COP0_SYNC - nop # required for QED5230 - nop # required for QED5230 - b 4f - nop -3: - mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask. - COP0_SYNC - _MTC0 a0, MIPS_COP_0_TLB_HI # init high reg. - COP0_SYNC - _MTC0 a2, MIPS_COP_0_TLB_LO0 # init low reg0. - COP0_SYNC - _MTC0 a1, MIPS_COP_0_TLB_LO1 # init low reg1. - COP0_SYNC - nop - nop # required for QED5230 - tlbwr # enter into a random slot - COP0_SYNC -4: # Make shure pipeline - nop # advances before we - nop # uses the tlb. - nop - nop - _MTC0 t0, MIPS_COP_0_TLB_HI # restore PID - COP0_SYNC - nop # required for QED5230 - nop # required for QED5230 - j ra - mtc0 v1, MIPS_COP_0_STATUS # Restore the status register - COP0_SYNC # XXXX - not executed!! -END(MIPSX(TLBUpdate)) - -/*-------------------------------------------------------------------------- - * * mipsN_TLBRead -- * * Read the TLB entry.