Date: Sat, 1 Jul 2023 17:20:47 GMT From: Warner Losh <imp@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 8e6ea10c3122 - main - superio+nctgpio: Add support for new (weird) chips Message-ID: <202307011720.361HKlH0066369@gitrepo.freebsd.org>
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The branch main has been updated by imp: URL: https://cgit.FreeBSD.org/src/commit/?id=8e6ea10c31220b5f56dbd966a0ee7163d46d30d1 commit 8e6ea10c31220b5f56dbd966a0ee7163d46d30d1 Author: Stéphane Rochoy <stephane.rochoy@stormshield.eu> AuthorDate: 2023-07-01 17:19:44 +0000 Commit: Warner Losh <imp@FreeBSD.org> CommitDate: 2023-07-01 17:19:52 +0000 superio+nctgpio: Add support for new (weird) chips Add support for the following chips: - Nuvoton NCT5585D - Nuvoton NCT6796D-E - Nuvoton NCT6779 - Nuvoton NCT6116D - and Winbond 83627DHG Reviewed by: imp Pull Request: https://github.com/freebsd/freebsd-src/pull/719 --- share/man/man4/nctgpio.4 | 16 +- share/man/man4/superio.4 | 6 + sys/dev/nctgpio/nctgpio.c | 511 +++++++++++++++++++++++++++++++++++++++++++++- sys/dev/superio/superio.c | 46 ++++- 4 files changed, 570 insertions(+), 9 deletions(-) diff --git a/share/man/man4/nctgpio.4 b/share/man/man4/nctgpio.4 index 54a0bdc2df2b..ff565319089c 100644 --- a/share/man/man4/nctgpio.4 +++ b/share/man/man4/nctgpio.4 @@ -1,11 +1,11 @@ .\" $FreeBSD$ .\" -.Dd Jan 11, 2021 +.Dd Apr 18, 2023 .Dt NCTGPIO 4 .Os .Sh NAME .Nm nctgpio -.Nd GPIO controller on Nuvoton and Winbond Super I/O +.Nd GPIO controller on Nuvoton and Winbond Super I/Os .Sh SYNOPSIS .Cd "device gpio" .Cd "device nctgpio" @@ -26,6 +26,16 @@ Nuvoton NCT5104D Nuvoton NCT5104D (PC-Engines APU) .It Nuvoton NCT5104D (PC-Engines APU3) +.It +Nuvoton NCT5585D +.It +Nuvoton NCT6116D +.It +Nuvoton NCT6779 +.It +Nuvoton NCT6796D-E +.It +Winbond 83627DHG .El .Sh SEE ALSO @@ -37,7 +47,7 @@ The driver first appeared in .Fx 11.0 . And the manual page first appeared in -.Fx 13.0 . +.Fx 14.0 . .Sh AUTHORS The driver was initially written by .An Daniel Wyatt Aq Mt daniel@dewyatt.com . diff --git a/share/man/man4/superio.4 b/share/man/man4/superio.4 index 548b93b713f8..2608f5331b05 100644 --- a/share/man/man4/superio.4 +++ b/share/man/man4/superio.4 @@ -111,6 +111,10 @@ Fintek F81865 .It Nuvoton NCT5104D/NCT6102D/NCT6106D rev. A and B+ .It +Nuvoton NCT5585D +.It +Nuvoton NCT6116D +.It Nuvoton NCT6775 .It Nuvoton NCT6776 @@ -125,6 +129,8 @@ Nuvoton NCT6793 .It Nuvoton NCT6795 .It +Nuvoton NCT6796D-E +.It Winbond 83627HF/F/HG/G/S/THF/EHF/DHG/UHG/DHG-P .It Winbond 83637HF diff --git a/sys/dev/nctgpio/nctgpio.c b/sys/dev/nctgpio/nctgpio.c index 607a5f3e56cf..fc3de033968f 100644 --- a/sys/dev/nctgpio/nctgpio.c +++ b/sys/dev/nctgpio/nctgpio.c @@ -150,6 +150,73 @@ struct nct_device { int ngroups; struct nct_gpio_group groups[NCT_MAX_GROUP + 1]; } nct_devices[] = { + { + .devid = 0xa025, + .descr = "GPIO on Winbond 83627DHG IC ver. 5", + .ngroups = 5, + .groups = { + { + .grpnum = 2, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x09, + .ppod_reg = 0xe0, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe3, + }, + { + .grpnum = 3, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x02, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf0, + }, + { + .grpnum = 4, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x04, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf4, + }, + { + .grpnum = 5, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x08, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe0, + }, + { + .grpnum = 6, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf4, + }, + }, + }, { .devid = 0x1061, .descr = "GPIO on Nuvoton NCT5104D", @@ -182,7 +249,7 @@ struct nct_device { }, }, { - .devid = 0xc452, + .devid = 0xc452, /* FIXME Conflict with Nuvoton NCT6106D. See NetBSD's nct_match. */ .descr = "GPIO on Nuvoton NCT5104D (PC-Engines APU)", .ngroups = 2, .groups = { @@ -243,6 +310,445 @@ struct nct_device { }, }, }, + { + .devid = 0xd42a, + .extid = 1, + .descr = "GPIO on Nuvoton NCT6796D-E", + .ngroups = 10, + .groups = { + { + .grpnum = 0, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x08, + .enable_reg = 0x30, + .enable_mask = 0x02, + .data_ldn = 0x08, + .ppod_reg = 0xe0, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe0, + }, + { + .grpnum = 1, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x08, + .enable_reg = 0x30, + .enable_mask = 0x80, + .data_ldn = 0x08, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf0, + }, + { + .grpnum = 2, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe0, + }, + { + .grpnum = 3, + .pinbits = { 0, 1, 2, 3, 4, 5, 6 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x02, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 7, + .iobase = 0xe4, + }, + { + .grpnum = 4, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x04, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf0, /* FIXME Page 344 say "F0~F2, E8", + not "F0~F3". */ + }, + { + .grpnum = 5, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x08, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf4, + }, + { + .grpnum = 6, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf4, + }, + { + .grpnum = 7, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x02, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe0, + }, + { + .grpnum = 8, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x04, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe4, + }, + { + .grpnum = 9, + .pinbits = { 0, 1, 2, 3 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x08, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 4, + .iobase = 0xe8, + }, + }, + }, + { + .devid = 0xd42a, + .extid = 2, + .descr = "GPIO on Nuvoton NCT5585D", + .ngroups = 6, + .groups = { + { + .grpnum = 2, + .pinbits = { 0, 1, 2, 3, 4, 5, 6 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x09, + .ppod_reg = 0xe1, + .caps = NCT_GPIO_CAPS, + .npins = 7, + .iobase = 0xe0, + }, + { + .grpnum = 3, + .pinbits = { 1, 2, 3 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x02, + .data_ldn = 0x09, + .ppod_reg = 0xe2, + .caps = NCT_GPIO_CAPS, + .npins = 3, + .iobase = 0xe4, + }, + { + .grpnum = 5, + .pinbits = { 0, 2, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x08, + .data_ldn = 0x09, + .ppod_reg = 0xe4, + .caps = NCT_GPIO_CAPS, + .npins = 4, + .iobase = 0xf4, + }, + { + .grpnum = 7, + .pinbits = { 4 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x02, + .data_ldn = 0x07, + .ppod_reg = 0xe6, + .caps = NCT_GPIO_CAPS, + .npins = 1, + .iobase = 0xe0, + }, + { + .grpnum = 8, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x04, + .data_ldn = 0x07, + .ppod_reg = 0xe7, + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe4, + }, + { + .grpnum = 9, + .pinbits = { 0, 2 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x08, + .data_ldn = 0x07, + .ppod_reg = 0xea, + .caps = NCT_GPIO_CAPS, + .npins = 2, + .iobase = 0xe8, + }, + }, + }, + { + .devid = 0xc562, + .descr = "GPIO on Nuvoton NCT6779D", + .ngroups = 9, + .groups = { + { + .grpnum = 0, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x08, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x08, + .ppod_reg = 0xe0, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe0, + }, + { + .grpnum = 1, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x08, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf0, + }, + { + .grpnum = 2, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe0, + }, + { + .grpnum = 3, + .pinbits = { 0, 1, 2, 3, 4, 5, 6 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x02, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 7, + .iobase = 0xe4, + }, + { + .grpnum = 4, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x04, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf0, + }, + { + .grpnum = 5, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x08, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf4, + }, + { + .grpnum = 6, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf4, + }, + { + .grpnum = 7, + .pinbits = { 0, 1, 2, 3, 4, 5, 6 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x02, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 7, + .iobase = 0xe0, + }, + { + .grpnum = 8, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x04, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe4, + }, + }, + }, + { + .devid = 0xd282, + .descr = "GPIO on Nuvoton NCT6112D/NCT6114D/NCT6116D", + .ngroups = 2, + .groups = { + { + .grpnum = 0, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x07, + .ppod_reg = 0xe0, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe0, + }, + { + .grpnum = 1, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x02, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe4, + }, + { + .grpnum = 2, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x04, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xe8, + }, + { + .grpnum = 3, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x08, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xec, + }, + { + .grpnum = 4, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x10, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf0, + }, + { + .grpnum = 5, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x20, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf4, + }, + { + .grpnum = 6, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x40, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf8, + }, + { + .grpnum = 7, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x07, + .enable_reg = 0x30, + .enable_mask = 0x80, + .data_ldn = 0x07, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xfc, + }, + { + .grpnum = 8, + .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, + .enable_ldn = 0x09, + .enable_reg = 0x30, + .enable_mask = 0x01, + .data_ldn = 0x09, + .ppod_reg = 0xe1, /* FIXME Need to check for this group. */ + .caps = NCT_GPIO_CAPS, + .npins = 8, + .iobase = 0xf0, + }, + }, + }, }; static const char * @@ -533,6 +1039,7 @@ nct_read_pin(struct nct_softc *sc, uint32_t pin_num) return (val); } +/* FIXME Incorret for NCT5585D and probably other chips. */ static uint8_t nct_ppod_reg(struct nct_softc *sc, uint32_t pin_num) { @@ -659,7 +1166,7 @@ nct_attach(device_t dev) sc->curgrp = -1; sc->iorid = 0; err = bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid, - iobase, 7); + iobase, 7); /* FIXME NCT6796D-E have 8 registers according to table 18.3. */ if (err == 0) { sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->iorid, RF_ACTIVE); diff --git a/sys/dev/superio/superio.c b/sys/dev/superio/superio.c index 6db2b0685c1c..2d40d9ef43b7 100644 --- a/sys/dev/superio/superio.c +++ b/sys/dev/superio/superio.c @@ -271,6 +271,12 @@ const struct sio_device ite_devices[] = { { .type = SUPERIO_DEV_NONE }, }; +const struct sio_device w83627_devices[] = { + { .ldn = 8, .type = SUPERIO_DEV_WDT }, + { .ldn = 9, .type = SUPERIO_DEV_GPIO }, + { .type = SUPERIO_DEV_NONE }, +}; + const struct sio_device nvt_devices[] = { { .ldn = 8, .type = SUPERIO_DEV_WDT }, { .type = SUPERIO_DEV_NONE }, @@ -283,6 +289,23 @@ const struct sio_device nct5104_devices[] = { { .type = SUPERIO_DEV_NONE }, }; +const struct sio_device nct5585_devices[] = { + { .ldn = 9, .type = SUPERIO_DEV_GPIO }, + { .type = SUPERIO_DEV_NONE }, +}; + +const struct sio_device nct611x_devices[] = { + { .ldn = 0x7, .type = SUPERIO_DEV_GPIO }, + { .ldn = 0x8, .type = SUPERIO_DEV_WDT }, + { .type = SUPERIO_DEV_NONE }, +}; + +const struct sio_device nct67xx_devices[] = { + { .ldn = 0x8, .type = SUPERIO_DEV_WDT }, + { .ldn = 0x9, .type = SUPERIO_DEV_GPIO }, + { .type = SUPERIO_DEV_NONE }, +}; + const struct sio_device fintek_devices[] = { { .ldn = 6, .type = SUPERIO_DEV_GPIO }, { .ldn = 7, .type = SUPERIO_DEV_WDT }, @@ -381,7 +404,7 @@ static const struct { { .vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa000, .mask = 0xff, .descr = "Winbond 83627DHG", - .devices = nvt_devices, + .devices = w83627_devices, }, { .vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa200, .mask = 0xff, @@ -419,9 +442,19 @@ static const struct { .devices = nct5104_devices, }, { - .vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc500, .mask = 0xff, - .descr = "Nuvoton NCT6779", - .devices = nvt_devices, + .vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc500, .mask = 0xff, + .descr = "Nuvoton NCT6779D", + .devices = nct67xx_devices, + }, + { + .vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 1, + .descr = "Nuvoton NCT6796D-E", + .devices = nct67xx_devices, + }, + { + .vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 2, + .descr = "Nuvoton NCT5585D", + .devices = nct5585_devices, }, { .vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc800, .mask = 0xff, @@ -438,6 +471,11 @@ static const struct { .descr = "Nuvoton NCT6793", .devices = nvt_devices, }, + { + .vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd200, .mask = 0xff, + .descr = "Nuvoton NCT6112D/NCT6114D/NCT6116D", + .devices = nct611x_devices, + }, { .vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd300, .mask = 0xff, .descr = "Nuvoton NCT6795",
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