From owner-cvs-src-old@FreeBSD.ORG Tue Oct 6 13:46:36 2009 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 31AAB1065693 for ; Tue, 6 Oct 2009 13:46:36 +0000 (UTC) (envelope-from attilio@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 1F0838FC12 for ; Tue, 6 Oct 2009 13:46:36 +0000 (UTC) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id n96DkaYD080027 for ; Tue, 6 Oct 2009 13:46:36 GMT (envelope-from attilio@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id n96DkZAn080026 for cvs-src-old@freebsd.org; Tue, 6 Oct 2009 13:46:35 GMT (envelope-from attilio@repoman.freebsd.org) Message-Id: <200910061346.n96DkZAn080026@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to attilio@repoman.freebsd.org using -f From: Attilio Rao Date: Tue, 6 Oct 2009 13:45:49 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/amd64/include atomic.h src/sys/i386/include atomic.h X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Oct 2009 13:46:36 -0000 attilio 2009-10-06 13:45:49 UTC FreeBSD src repository Modified files: sys/amd64/include atomic.h sys/i386/include atomic.h Log: SVN rev 197803 on 2009-10-06 13:45:49Z by attilio Per their definition, atomic instructions used in conjuction with memory barriers should also ensure that the compiler doesn't reorder paths where they are used. GCC, however, does that aggressively, even in presence of volatile operands. The most reliable way GCC offers for avoid instructions reordering is clobbering "memory" even if that is theoretically an heavy-weight operation, flushing the content of all the registers and forcing reload of them (We could rely, however, on gcc DTRT by just understanding the purpose as this is a well-known pattern for many modern operating-systems). Not all our memory barriers, right now, clobber memory for GCC-like compilers. The most notable cases are IA32 and amd64 where the memory barrier are treacted the same as normal atomic instructions. Fix this by offering the possibility to implement atomic instructions with memory barriers separately from the normal version and implement the GCC-like specific one using memory clobbering. Thanks to Chris Lattner (@apple) for his discussion on llvm specifics. Reported by: jhb Reviewed by: jhb Tested by: rdivacky, Giovanni Trematerra Revision Changes Path 1.47 +67 -46 src/sys/amd64/include/atomic.h 1.52 +73 -46 src/sys/i386/include/atomic.h