From owner-freebsd-current@FreeBSD.ORG Wed Jun 16 16:56:56 2004 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 06E6216A4CE for ; Wed, 16 Jun 2004 16:56:56 +0000 (GMT) Received: from mailout09.sul.t-online.com (mailout09.sul.t-online.com [194.25.134.84]) by mx1.FreeBSD.org (Postfix) with ESMTP id 9B70643D1F for ; Wed, 16 Jun 2004 16:56:55 +0000 (GMT) (envelope-from Alexander@Leidinger.net) Received: from fwd10.aul.t-online.de by mailout09.sul.t-online.com with smtp id 1Badi3-0005Jz-02; Wed, 16 Jun 2004 18:56:23 +0200 Received: from Andro-Beta.Leidinger.net (rXDkVgZCgeK4Db9Vn+JlkvP6r1fkuO8egxME+D17946HD4567S5pUn@[217.229.221.168]) by fmrl10.sul.t-online.com with esmtp id 1Badhj-106Zqi0; Wed, 16 Jun 2004 18:56:03 +0200 Received: from Magellan.Leidinger.net (Magellan.Leidinger.net [192.168.1.1]) i5GGuHC8005835; Wed, 16 Jun 2004 18:56:17 +0200 (CEST) (envelope-from Alexander@Leidinger.net) Date: Wed, 16 Jun 2004 18:57:57 +0200 From: Alexander Leidinger To: John Polstra Message-Id: <20040616185757.4b19ea3e@Magellan.Leidinger.net> In-Reply-To: References: <40D07430.1070504@raadradd.com> X-Mailer: Sylpheed version 0.9.11claws (GTK+ 1.2.10; i386-portbld-freebsd5.2) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Seen: false X-ID: rXDkVgZCgeK4Db9Vn+JlkvP6r1fkuO8egxME+D17946HD4567S5pUn@t-dialin.net cc: current@freebsd.org cc: Radek Kozlowski Subject: Re: How to determine the L2 cache size on non-AMD CPUs (automatic page queue color tuning)? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Jun 2004 16:56:56 -0000 On Wed, 16 Jun 2004 09:35:40 -0700 (PDT) John Polstra wrote: > On 16-Jun-2004 Radek Kozlowski wrote: > > The latest version of cpuid is from 2002 and at least for my Athlon XP-M > > processor it doesn't read the information about L2 cache correctly. > > IIRC, for my L2 size it only takes one byte from the beginning of ecx > > register, whereas in my case it is stored in two, a.s.o. So I wouldn't > > rely on cpuid when it comes to newer CPUs. If bootverbose prints the cache size correctly (at least on -current), I already have code which does the right thing for your AMD CPU. > Yes, but it gives working code that generally shows how to get the > information. Here's a link to an Intel document "Intel(R) Processor > Idientification and the CPUID Instruction" that covers the newer CPUs: > > http://www.intel.com/design/Xeon/applnots/24161825.pdf I will have a look at both (the cpuid port and the PDF). Thanks, Alexander. -- I'm available to get hired (preferred in .lu). http://www.Leidinger.net Alexander @ Leidinger.net GPG fingerprint = C518 BC70 E67F 143F BE91 3365 79E2 9C60 B006 3FE7