From owner-freebsd-hackers@FreeBSD.ORG Sun Feb 17 17:09:58 2008 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id AB48C16A418 for ; Sun, 17 Feb 2008 17:09:58 +0000 (UTC) (envelope-from avg@icyb.net.ua) Received: from falcon.cybervisiontech.com (falcon.cybervisiontech.com [217.20.163.9]) by mx1.freebsd.org (Postfix) with ESMTP id 60CA413C4CC for ; Sun, 17 Feb 2008 17:09:58 +0000 (UTC) (envelope-from avg@icyb.net.ua) Received: from localhost (localhost [127.0.0.1]) by falcon.cybervisiontech.com (Postfix) with ESMTP id 6AB22744005; Sun, 17 Feb 2008 19:09:57 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at falcon.cybervisiontech.com Received: from falcon.cybervisiontech.com ([127.0.0.1]) by localhost (falcon.cybervisiontech.com [127.0.0.1]) (amavisd-new, port 10027) with ESMTP id y06v9k6xmSJR; Sun, 17 Feb 2008 19:09:57 +0200 (EET) Received: from [10.74.70.239] (unknown [193.138.145.53]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by falcon.cybervisiontech.com (Postfix) with ESMTP id C4A36744004; Sun, 17 Feb 2008 19:09:56 +0200 (EET) Message-ID: <47B86A63.1040205@icyb.net.ua> Date: Sun, 17 Feb 2008 19:09:55 +0200 From: Andriy Gapon User-Agent: Thunderbird 2.0.0.9 (X11/20071208) MIME-Version: 1.0 To: Erich Dollansky References: <47B855C0.4010703@icyb.net.ua> <47B85E92.9010206@pacific.net.sg> In-Reply-To: <47B85E92.9010206@pacific.net.sg> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Cc: freebsd-hackers@freebsd.org Subject: Re: multiple interrupts between cli and sti X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Feb 2008 17:09:58 -0000 on 17/02/2008 18:19 Erich Dollansky said the following: > Hi, > > Andriy Gapon wrote: > > I cannot tell you if this is still the same for modern designs. > >> ... -> iret -> interrupted again > > This was the behaviour earlier. >> Is this a deterministic behavior ? Or some timings are at play? > > The PIC should never release the Interrupt signal to the CPU as long as > a single interrupt is not serviced. > > But the 8259 can be programmed to trigger via level or slope. > > So, this behaviour is only seen when level triggering is used. > > As I said at the bginning, I do not know how current designs handle it. But I thought level/edge thing is about interrupts between devices and PIC, not between PIC and CPU. I might be confused, though. -- Andriy Gapon