Date: Thu, 12 Sep 1996 17:07:15 -0600 From: Steve Passe <smp@csn.net> To: erich@uruk.org Cc: terry@lambert.org, peter@spinner.dialix.com, rv@groa.uct.ac.za, freebsd-smp@freebsd.org Subject: Re: (long) Intel SMP info (was -> Re: Intel XXpress - some SMP benchmarks) Message-ID: <199609122307.RAA20132@clem.systemsix.com> In-Reply-To: Your message of "Thu, 12 Sep 1996 14:13:44 PDT." <199609122113.OAA13651@uruk.org>
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Hi,
erich, thanx for helping!
---
> Also realize that when a processor goes through INIT, the APIC id will be
> reset to the hardware id. This means if your OS is in the middle of doing
pentium processor manual vol3, 19.3.1.11.3 'Initialization Reset (INIT)':
"INIT is a software reset, and is delivered as a bus message. INIT has
the same effect on the Local APIC as the power-up Reset, except that the
APIC ID and the Arb ID registers are not affected."
---
> Before your operation, write a zero to the APIC_ESR register (I think a
> read before the write is even necessary... I'll dredge up my notes
> which tried to make sense of all the eratta sometime tonight or tomorrow).
I followed your code from the linux project for accessing the ESR register,
including the clear of the register to start.
---------------------------------------------
Everyone please bear with me here, this gets ugly,
but I think we are getting close to resolution.
---
> It's not a problem of the first STARTUP being "missed", the problem
> (which is only present on the Pentium integrated APIC) is as follows:
> When the Pentium is in the state waiting for a STARTUP, an INIT
"in the state waiting for a STARTUP", is this a state reached by hardware
RESET? or perhaps I'm asking what this state is. Is it as if a 'hlt'
instruction had been executed?
> doesn't get processed, but it is latched. The STARTUP then allows the
> INIT to be executed, which effectively kills the STARTUP message (this is
> where the time-delays in the recommended INIT/STARTUP/STARTUP process
> come from, to allow the CPU to finish the INIT process), so you need
> another STARTUP message.
so if I understand this we have:
2nd CPU is waiting for a STARTUP IPI
1st CPU does INIT,
1st CPU waits for INIT
to run
2nd CPU latches INIT IPI, DOESN'T process it yet.
1st CPU finishes wait
1st CPU does STARTUP IPI
2nd CPU catches STARTUP IPI,
starts to vector thru supplied STARTUP vector
2nd CPU immediately catches INIT IPI,
aborting STARTUP IPI
INIT causes vector thru warm-boot to bootMP()
bootMP() gets 2nd CPU initialized and running
2nd CPU ignores second STARTUP IPI as it only
accepts ONE STARTUP IPI after RESET/INIT
to get the XXPRESS box working I HAD to preceed the INIT IPI with
a setup of the BIOS warm-start vector to the bootMP() code.
pointing it at a 'hlt' instruction, then allowing the STARTUP IPI to
provide the vector to bootMP() fails. so it would appear that BOTH
of the STARTUP IPIs (both vectoring to bootMP()) fail and/or are
ignored by the XXPRESS. I'm sure (he says with confidence) that the INIT
IPI actually travels thru the vector as we replaced the 'hlt' instruction with
an NMI and we got spontanious reboot.
> The problem with trying to just do an INIT, then if that doesn't work, a
> STARTUP and INIT, is that you're never sure what the state the BIOS
> puts CPUs in on a lot of the Pentium boxes (you'd also have to wait
> to see if it responded to each part of the sequence). I spent a lot of
> time finding out that the ENTIRE sequence was required on even machines
> that I thought didn't need it (the XXPress box). The Intel folks
> spent a lot of time generating a single guaranteed sequence that
> covered all the bases.
I'm getting a headache... SO at this point I think I buy the double
INIT IPI followed by 2 STARTUP IPS, with appropriate timings in-between
as the cure for all hardware, in all the "brokenness" we are likely to find.
I'm just not clear on the appropriate thing to do with the warm-start vector.
I believe its needed, and that the XXPRESS for one needs it to point to
the actual 2nd CPU boot code. Can we expect to be able to vector to
the boot code on all hardware, or will we encounter boxes that run the
boot code via the INIT IPI warm-start vector, then re-run it via one
of the following STARTUP IPIs???????
is there a definitive code sample that encompasses all this. in the
MP spec they have the pseudo code with 2 STARTUP IPIs, but no actual code.
the pentium manual shows some real code with timings, but NO double
STARTUP sequence....
Peter, if this is whats happening to you with the new apic_startup()
I submitted, cloning the STARTUP+delay+read pending section to a 2nd one
should fix it (I think).
--
Steve Passe | powered by
smp@csn.net | FreeBSD
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