From owner-svn-src-all@FreeBSD.ORG Fri Oct 7 06:13:39 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 012EB106566C; Fri, 7 Oct 2011 06:13:39 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id E55E08FC17; Fri, 7 Oct 2011 06:13:38 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p976DcVI096178; Fri, 7 Oct 2011 06:13:38 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p976DcIh096176; Fri, 7 Oct 2011 06:13:38 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201110070613.p976DcIh096176@svn.freebsd.org> From: Adrian Chadd Date: Fri, 7 Oct 2011 06:13:38 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r226091 - head/sys/dev/hwpmc X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 07 Oct 2011 06:13:39 -0000 Author: adrian Date: Fri Oct 7 06:13:38 2011 New Revision: 226091 URL: http://svn.freebsd.org/changeset/base/226091 Log: Begin implementing correct MIPS24K sampling mode behaviour. * Add the interrupt bit in the configuration register * Correctly set the counter register for the sampling overflow interrupt. The interrupt is asserted when bit 31 is set. So set the overflow value at 0x80000000 and subtract the programmed value as appropriate. Modified: head/sys/dev/hwpmc/hwpmc_mips24k.h Modified: head/sys/dev/hwpmc/hwpmc_mips24k.h ============================================================================== --- head/sys/dev/hwpmc/hwpmc_mips24k.h Fri Oct 7 06:00:00 2011 (r226090) +++ head/sys/dev/hwpmc/hwpmc_mips24k.h Fri Oct 7 06:13:38 2011 (r226091) @@ -35,7 +35,7 @@ PMC_CAP_WRITE | PMC_CAP_INVERT | \ PMC_CAP_QUALIFIER) - +#define MIPS24K_PMC_INTERRUPT_ENABLE 0x10 /* Enable interrupts */ #define MIPS24K_PMC_USER_ENABLE 0x08 /* Count in USER mode */ #define MIPS24K_PMC_SUPER_ENABLE 0x04 /* Count in SUPERVISOR mode */ #define MIPS24K_PMC_KERNEL_ENABLE 0x02 /* Count in KERNEL mode */ @@ -43,9 +43,12 @@ MIPS24K_PMC_SUPER_ENABLE | \ MIPS24K_PMC_KERNEL_ENABLE) - -#define MIPS24K_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R)) -#define MIPS24K_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) +/* + * Interrupts are posted when bit 31 of the relevant + * counter is set. + */ +#define MIPS24K_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (0x80000000 - (R)) +#define MIPS24K_PERFCTR_VALUE_TO_RELOAD_COUNT(P) ((P) - 0x80000000) #define MIPS24K_PMC_SELECT 0x4 /* Which bit position the event starts at. */ #define MIPS24K_PMC_OFFSET 2 /* Control registers are 0, 2, 4, etc. */