From owner-svn-src-head@freebsd.org Wed Jun 1 14:12:32 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E9701B4F2F1; Wed, 1 Jun 2016 14:12:32 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id AC09811D8; Wed, 1 Jun 2016 14:12:32 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u51ECVwT080944; Wed, 1 Jun 2016 14:12:31 GMT (envelope-from br@FreeBSD.org) Received: (from br@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u51ECVi8080942; Wed, 1 Jun 2016 14:12:31 GMT (envelope-from br@FreeBSD.org) Message-Id: <201606011412.u51ECVi8080942@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: br set sender to br@FreeBSD.org using -f From: Ruslan Bukin Date: Wed, 1 Jun 2016 14:12:31 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r301126 - in head/sys/riscv: conf riscv X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Jun 2016 14:12:33 -0000 Author: br Date: Wed Jun 1 14:12:31 2016 New Revision: 301126 URL: https://svnweb.freebsd.org/changeset/base/301126 Log: Add support for loadable kernel modules. Submitted by: Yukishige Shibata Modified: head/sys/riscv/conf/GENERIC head/sys/riscv/riscv/elf_machdep.c Modified: head/sys/riscv/conf/GENERIC ============================================================================== --- head/sys/riscv/conf/GENERIC Wed Jun 1 14:11:40 2016 (r301125) +++ head/sys/riscv/conf/GENERIC Wed Jun 1 14:12:31 2016 (r301126) @@ -23,7 +23,9 @@ ident GENERIC makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols # makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support -makeoptions NO_MODULES=1 # We don't yet support modules on RISC-V + +# FIXME: linker error. "--relax and -r may not be used together" +makeoptions WITHOUT_MODULES="usb otusfw mwlfw ispfw mwlfw ralfw rtwnfw urtwnfw" options SCHED_ULE # ULE scheduler options PREEMPTION # Enable kernel thread preemption Modified: head/sys/riscv/riscv/elf_machdep.c ============================================================================== --- head/sys/riscv/riscv/elf_machdep.c Wed Jun 1 14:11:40 2016 (r301125) +++ head/sys/riscv/riscv/elf_machdep.c Wed Jun 1 14:12:31 2016 (r301126) @@ -1,6 +1,7 @@ /*- * Copyright 1996-1998 John D. Polstra. * Copyright (c) 2015 Ruslan Bukin + * Copyright (c) 2016 Yukishige SHibata * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -43,6 +44,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -123,19 +125,380 @@ SYSINIT(oelf64, SI_SUB_EXEC, SI_ORDER_AN (sysinit_cfunc_t) elf64_insert_brand_entry, &freebsd_brand_oinfo); +static int debug_kld; +SYSCTL_INT(_kern, OID_AUTO, debug_kld, + CTLFLAG_RW, &debug_kld, 0, + "Activate debug prints in elf_reloc_internal()"); + +struct type2str_ent { + int type; + const char* str; +}; + void elf64_dump_thread(struct thread *td, void *dst, size_t *off) { } -/* Process one elf relocation with addend. */ +/* + * Following 4 functions are used to manupilate bits on 32bit interger value. + * FIXME: I implemetend for ease-to-understand rather than for well-optimized. + */ +static uint32_t +gen_bitmask(int msb, int lsb) +{ + uint32_t mask; + + if (msb == sizeof(mask) * 8 - 1) + mask = ~0; + else + mask = (1U << (msb + 1)) - 1; + + if (lsb > 0) + mask &= ~((1U << lsb) - 1); + + return (mask); +} + +static uint32_t +extract_bits(uint32_t x, int msb, int lsb) +{ + uint32_t mask; + + mask = gen_bitmask(msb, lsb); + + x &= mask; + x >>= lsb; + + return (x); +} + +static uint32_t +insert_bits(uint32_t d, uint32_t s, int msb, int lsb) +{ + uint32_t mask; + + mask = gen_bitmask(msb, lsb); + + d &= ~mask; + + s <<= lsb; + s &= mask; + + return (d | s); +} + +static uint32_t +insert_imm(uint32_t insn, uint32_t imm, int imm_msb, int imm_lsb, + int insn_lsb) +{ + int insn_msb; + uint32_t v; + + v = extract_bits(imm, imm_msb, imm_lsb); + insn_msb = (imm_msb - imm_lsb) + insn_lsb; + + return (insert_bits(insn, v, insn_msb, insn_lsb)); +} + +/* + * The RISCV ISA is designed so that all of immediate value is + * sign-extened. + * An immediate value is sometimes generated at runtime by adding + * 12bit sign integer and 20bit signed integer. This requests 20bit + * immediate value to be ajusted if the MSB of the 12bit immediate + * value is asserted (sign extened value is treated as negative value). + * + * For example, 0x123800 can be calculated by adding upper 20 bit of + * 0x124000 and signed-extended 12bit immediate whose bit pattern is + * 0x800 as follows; + * 0x123800 + * = 0x123000 + 0x800 + * = (0x123000 + 0x1000) + (-0x1000 + 0x800) + * = (0x123000 + 0x1000) + (0xff...ff800) + * = 0x124000 + sign-exntend(0x800) + */ +static uint32_t +calc_hi20_imm(uint32_t value) +{ + /* + * There is the arithmetical hack that can remove conditional + * statement. But I implement it in straghtforward way. + */ + if ((value & 0x800) != 0) + value += 0x1000; + return (value & ~0xfff); +} + +static const struct type2str_ent t2s[] = { + { R_RISCV_NONE, "R_RISCV_NONE" }, + { R_RISCV_64, "R_RISCV_64" }, + { R_RISCV_JUMP_SLOT, "R_RISCV_JUMP_SLOT" }, + { R_RISCV_RELATIVE, "R_RISCV_RELATIVE" }, + { R_RISCV_JAL, "R_RISCV_JAL" }, + { R_RISCV_CALL, "R_RISCV_CALL" }, + { R_RISCV_PCREL_HI20, "R_RISCV_PCREL_HI20" }, + { R_RISCV_PCREL_LO12_I, "R_RISCV_PCREL_LO12_I" }, + { R_RISCV_PCREL_LO12_S, "R_RISCV_PCREL_LO12_S" }, + { R_RISCV_HI20, "R_RISCV_HI20" }, + { R_RISCV_LO12_I, "R_RISCV_LO12_I" }, + { R_RISCV_LO12_S, "R_RISCV_LO12_S" }, +}; + +static const char* +reloctype_to_str(int type) +{ + int i; + + for (i = 0; i < sizeof(t2s) / sizeof(t2s[0]); ++i) { + if (type == t2s[i].type) + return t2s[i].str; + } + + return "*unknown*"; +} + +/* + * Currently kernel loadable module for RISCV is compiled with -fPIC option. + * (see also additional CFLAGS definition for RISCV in sys/conf/kmod.mk) + * Only R_RISCV_64, R_RISCV_JUMP_SLOT and RISCV_RELATIVE are emitted in + * the module. Other relocations will be processed when kernel loadable + * modules are built in non-PIC. + * + * FIXME: only RISCV64 is supported. + */ static int elf_reloc_internal(linker_file_t lf, Elf_Addr relocbase, const void *data, int type, int local, elf_lookup_fn lookup) { + Elf_Size rtype, symidx; + const Elf_Rela *rela; + Elf_Addr val, addr; + Elf64_Addr *where; + Elf_Addr addend; + uint32_t before32_1; + uint32_t before32; + uint64_t before64; + uint32_t* insn32p; + uint32_t imm20; + int error; + + switch (type) { + case ELF_RELOC_RELA: + rela = (const Elf_Rela *)data; + where = (Elf_Addr *)(relocbase + rela->r_offset); + insn32p = (uint32_t*)where; + addend = rela->r_addend; + rtype = ELF_R_TYPE(rela->r_info); + symidx = ELF_R_SYM(rela->r_info); + break; + default: + printf("%s:%d unknown reloc type %d\n", + __FUNCTION__, __LINE__, type); + return -1; + } + + switch (rtype) { + case R_RISCV_NONE: + break; + + case R_RISCV_64: + case R_RISCV_JUMP_SLOT: + error = lookup(lf, symidx, 1, &addr); + if (error != 0) + return -1; + + val = addr; + before64 = *where; + if (*where != val) + *where = val; + + if (debug_kld) + printf("%p %c %-24s %016lx -> %016lx\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before64, *where); + break; + + case R_RISCV_RELATIVE: + val = relocbase + addend; + + before64 = *where; + if (*where != val) + *where = val; + + if (debug_kld) + printf("%p %c %-24s %016lx -> %016lx\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before64, *where); + break; + + case R_RISCV_JAL: + error = lookup(lf, symidx, 1, &addr); + if (error != 0) + return -1; + + val = addr - (Elf_Addr)where; + if ((val <= -(1UL << 20) || (1UL << 20) <= val)) { + printf("kldload: huge offset against R_RISCV_JAL\n"); + return -1; + } + + before32 = *insn32p; + *insn32p = insert_imm(*insn32p, val, 20, 20, 31); + *insn32p = insert_imm(*insn32p, val, 10, 1, 21); + *insn32p = insert_imm(*insn32p, val, 11, 11, 20); + *insn32p = insert_imm(*insn32p, val, 19, 12, 12); + + if (debug_kld) + printf("%p %c %-24s %08x -> %08x\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before32, *insn32p); + break; + + case R_RISCV_CALL: + /* + * R_RISCV_CALL relocates 8-byte region that consists + * of the sequence of AUIPC and JALR. + */ + /* calculate and check the pc relative offset. */ + error = lookup(lf, symidx, 1, &addr); + if (error != 0) + return -1; + val = addr - (Elf_Addr)where; + if ((val <= -(1UL << 32) || (1UL << 32) <= val)) { + printf("kldload:%s: huge offset against R_RISCV_CALL\n"); + return -1; + } + + /* Relocate AUIPC. */ + before32 = insn32p[0]; + imm20 = calc_hi20_imm(val); + insn32p[0] = insert_imm(insn32p[0], imm20, 31, 12, 12); + + /* Relocate JALR. */ + before32_1 = insn32p[1]; + insn32p[1] = insert_imm(insn32p[1], val, 11, 0, 20); + + if (debug_kld) + printf("%p %c %-24s %08x %08x -> %08x %08x\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before32, insn32p[0], + before32_1, insn32p[1]); + break; + + case R_RISCV_PCREL_HI20: + val = addr - (Elf_Addr)where; + insn32p = (uint32_t*)where; + before32 = *insn32p; + imm20 = calc_hi20_imm(val); + *insn32p = insert_imm(*insn32p, imm20, 31, 12, 12); + + if (debug_kld) + printf("%p %c %-24s %08x -> %08x\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before32, *insn32p); + break; + + case R_RISCV_PCREL_LO12_I: + val = addr - (Elf_Addr)where; + insn32p = (uint32_t*)where; + before32 = *insn32p; + *insn32p = insert_imm(*insn32p, addr, 11, 0, 20); + + if (debug_kld) + printf("%p %c %-24s %08x -> %08x\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before32, *insn32p); + break; + + case R_RISCV_PCREL_LO12_S: + val = addr - (Elf_Addr)where; + insn32p = (uint32_t*)where; + before32 = *insn32p; + *insn32p = insert_imm(*insn32p, addr, 11, 5, 25); + *insn32p = insert_imm(*insn32p, addr, 4, 0, 7); + if (debug_kld) + printf("%p %c %-24s %08x -> %08x\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before32, *insn32p); + break; + + case R_RISCV_HI20: + error = lookup(lf, symidx, 1, &addr); + if (error != 0) + return -1; + + insn32p = (uint32_t*)where; + before32 = *insn32p; + imm20 = calc_hi20_imm(val); + *insn32p = insert_imm(*insn32p, imm20, 31, 12, 12); + + if (debug_kld) + printf("%p %c %-24s %08x -> %08x\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before32, *insn32p); + break; + + case R_RISCV_LO12_I: + error = lookup(lf, symidx, 1, &addr); + if (error != 0) + return -1; + + val = addr; + insn32p = (uint32_t*)where; + before32 = *insn32p; + *insn32p = insert_imm(*insn32p, addr, 11, 0, 20); + + if (debug_kld) + printf("%p %c %-24s %08x -> %08x\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before32, *insn32p); + break; + + case R_RISCV_LO12_S: + error = lookup(lf, symidx, 1, &addr); + if (error != 0) + return -1; + + val = addr; + insn32p = (uint32_t*)where; + before32 = *insn32p; + *insn32p = insert_imm(*insn32p, addr, 11, 5, 25); + *insn32p = insert_imm(*insn32p, addr, 4, 0, 7); + + if (debug_kld) + printf("%p %c %-24s %08x -> %08x\n", + where, + (local? 'l': 'g'), + reloctype_to_str(rtype), + before32, *insn32p); + break; + + default: + printf("kldload: unexpected relocation type %ld\n", rtype); + return (-1); + } - panic("elf_reloc_internal"); + return (0); } int