From owner-svn-src-head@freebsd.org Thu Dec 7 10:03:46 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id CFD92E82301; Thu, 7 Dec 2017 10:03:46 +0000 (UTC) (envelope-from danfe@freebsd.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2610:1c1:1:6074::16:84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "freefall.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id AEA1A7FC04; Thu, 7 Dec 2017 10:03:46 +0000 (UTC) (envelope-from danfe@freebsd.org) Received: by freefall.freebsd.org (Postfix, from userid 1033) id 037BA1F67E; Thu, 7 Dec 2017 10:03:45 +0000 (UTC) Date: Thu, 7 Dec 2017 10:03:45 +0000 From: Alexey Dokuchaev To: Jung-uk Kim Cc: cem@freebsd.org, svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers Subject: Re: svn commit: r326383 - head/sys/x86/cpufreq Message-ID: <20171207100345.GA59559@FreeBSD.org> References: <201711300140.vAU1e7dC001292@repo.freebsd.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.1 (2017-09-22) X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Dec 2017 10:03:46 -0000 On Thu, Nov 30, 2017 at 03:08:49PM -0500, Jung-uk Kim wrote: > ... > Probably. However, I am just trying to fix my FX-8350 and A10-6800 and > I don't have Zen processors to verify the MSRs are actually working on > those CPUs. Ah, that's so lovely, thanks Jung-uk; I feel that our support for AMD fam. 15h CPUs is lacking. E.g. only four P-states are reported for my A8-5550M, while it supports boosted P-states per BKDG, and reading MSRs directly via `sysutils/amdmsrtweaker' reports eight of them (P0 .. P7), with three turbo P-states P0 P1 P2. Since you have A10-6800 you might try to reproduce what I see here with A8-5550M. ./danfe