From owner-svn-src-all@freebsd.org Wed Mar 13 20:37:03 2019 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id DCC8D1541748; Wed, 13 Mar 2019 20:37:02 +0000 (UTC) (envelope-from cse.cem@gmail.com) Received: from mail-io1-f50.google.com (mail-io1-f50.google.com [209.85.166.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "GTS CA 1O1" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 81C616F9D3; Wed, 13 Mar 2019 20:37:02 +0000 (UTC) (envelope-from cse.cem@gmail.com) Received: by mail-io1-f50.google.com with SMTP id x4so2964172ion.2; Wed, 13 Mar 2019 13:37:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:reply-to :from:date:message-id:subject:to:cc; bh=D9xWOUv3OfQQ7pBLU4Ila9Cpw1QMZuA31AyESu/kZp0=; b=RlxNyIKv34dObOw60wMHCm2ggT5cpzsInJCYgl1Ctm2E6ghKqsaWj1dnR2d7vqYfpP wuO17FDIganMf8+3JfXc5Hx1vOAiTuNnTuZ87tf5zzdxnrvEuf5DanKK2fPYsjRUyJ63 Jgwhr+3ErRjMwKqQ+DuoH4O+Se1rAy+55eg3Yaap9jlbfMpy4nJA8hlSzV3T0FVQn0qS mMhFGiLtqJoanlYMBpbGNb0lZ1G8DeVBsEvg/Oe2piChDLgI8rAnaos49gKX+Rk7zPNJ oUAOobw+T2v3QjmIyrgH/qBjbl/r42mDVjH9cOguMRdax8izhQGrGv6CVfqox6B/PrOz gKjA== X-Gm-Message-State: APjAAAW6mDr0bZ2r6YaM1c2K0dm+V2b3aoA+w0OARtCbrmWk4+4l/DkG 0ESyXGK5O06jTkDX4/Z/fbUVqDHi X-Google-Smtp-Source: APXvYqyJFLD0rvuvhSIItKM32jlesn11Sf8IuPJVdI5dlM+o166jXab0i/XZ9pqkriTlZsBxUNvuRw== X-Received: by 2002:a5e:dd44:: with SMTP id u4mr5755409iop.44.1552509416303; Wed, 13 Mar 2019 13:36:56 -0700 (PDT) Received: from mail-io1-f48.google.com (mail-io1-f48.google.com. [209.85.166.48]) by smtp.gmail.com with ESMTPSA id a8sm4113608iol.35.2019.03.13.13.36.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Mar 2019 13:36:55 -0700 (PDT) Received: by mail-io1-f48.google.com with SMTP id f6so2971197iop.3; Wed, 13 Mar 2019 13:36:55 -0700 (PDT) X-Received: by 2002:a5e:a710:: with SMTP id b16mr8377098iod.233.1552509415750; Wed, 13 Mar 2019 13:36:55 -0700 (PDT) MIME-Version: 1.0 References: <201903131915.x2DJFbRk002502@repo.freebsd.org> In-Reply-To: <201903131915.x2DJFbRk002502@repo.freebsd.org> Reply-To: cem@freebsd.org From: Conrad Meyer Date: Wed, 13 Mar 2019 13:36:45 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: svn commit: r345103 - head/sys/compat/linuxkpi/common/include/linux To: Hans Petter Selasky , Johannes Lundberg Cc: src-committers , svn-src-all , svn-src-head Content-Type: text/plain; charset="UTF-8" X-Rspamd-Queue-Id: 81C616F9D3 X-Spamd-Bar: ------ Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-6.98 / 15.00]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; REPLY(-4.00)[]; NEURAL_HAM_SHORT(-0.98)[-0.980,0]; TAGGED_FROM(0.00)[] X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Mar 2019 20:37:03 -0000 Hi, A lot of the information about PCIe devices is read by PCI probe and cached on the (BSD) device. You could access it out of device_get_ivars(bsddev)->cfg.pcie and avoid the MMIO latency. On Wed, Mar 13, 2019 at 12:15 PM Hans Petter Selasky wrote: > +static inline enum pci_bus_speed > +pcie_get_speed_cap(struct pci_dev *dev) > +{ > + device_t root; > + uint32_t lnkcap, lnkcap2; > + int error, pos; > + > + root = device_get_parent(dev->dev.bsddev); > + if (root == NULL) > + return (PCI_SPEED_UNKNOWN); > + root = device_get_parent(root); > + if (root == NULL) > + return (PCI_SPEED_UNKNOWN); > + root = device_get_parent(root); > + if (root == NULL) > + return (PCI_SPEED_UNKNOWN); What is this mechanism trying to accomplish? It seems incredibly fragile. Looking for pci0? pcib0? > + if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) > + return (PCI_SPEED_UNKNOWN); Cached as non-zero cfg.pcie.pcie_location value in ivars. > + lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); This one we don't cache, unfortunately, but could. Ditto LINK_CAP below. Usually "pos + PCIEfoo" is spelled "pcie_read_config(..., PCIEfoo...)." > + > + if (lnkcap2) { /* PCIe r3.0-compliant */ > + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) > + return (PCIE_SPEED_2_5GT); Seems like these definitions would be better suited as native PCIEM_LINK_CAP2_foo definitions in pcireg.h > + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) > + return (PCIE_SPEED_5_0GT); > + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) > + return (PCIE_SPEED_8_0GT); > + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) > + return (PCIE_SPEED_16_0GT); > + } else { /* pre-r3.0 */ > + lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); > + if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) > + return (PCIE_SPEED_2_5GT); > + if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) > + return (PCIE_SPEED_5_0GT); > + if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) > + return (PCIE_SPEED_8_0GT); > + if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) > + return (PCIE_SPEED_16_0GT); > + } > + return (PCI_SPEED_UNKNOWN); > +} > + > +static inline enum pcie_link_width > +pcie_get_width_cap(struct pci_dev *dev) > +{ > + uint32_t lnkcap; > + > + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); Better spelled as PCIER_LINK_CAP. > + if (lnkcap) > + return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); And PCIEM_LINK_CAP_MAX_WIDTH. > + > + return (PCIE_LNK_WIDTH_UNKNOWN); > } > > #endif /* _LINUX_PCI_H_ */ > Best, Conrad