From owner-svn-src-projects@FreeBSD.ORG Tue Oct 27 23:45:48 2009 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id D7F591065676; Tue, 27 Oct 2009 23:45:48 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id C78018FC19; Tue, 27 Oct 2009 23:45:48 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n9RNjmVu045003; Tue, 27 Oct 2009 23:45:48 GMT (envelope-from gonzo@svn.freebsd.org) Received: (from gonzo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n9RNjmfh045002; Tue, 27 Oct 2009 23:45:48 GMT (envelope-from gonzo@svn.freebsd.org) Message-Id: <200910272345.n9RNjmfh045002@svn.freebsd.org> From: Oleksandr Tymoshenko Date: Tue, 27 Oct 2009 23:45:48 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r198530 - projects/mips/sys/mips/mips X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Oct 2009 23:45:48 -0000 Author: gonzo Date: Tue Oct 27 23:45:48 2009 New Revision: 198530 URL: http://svn.freebsd.org/changeset/base/198530 Log: - Replace stubs with actual cache info - minor style(9) fix Modified: projects/mips/sys/mips/mips/cache.c Modified: projects/mips/sys/mips/mips/cache.c ============================================================================== --- projects/mips/sys/mips/mips/cache.c Tue Oct 27 21:09:52 2009 (r198529) +++ projects/mips/sys/mips/mips/cache.c Tue Oct 27 23:45:48 2009 (r198530) @@ -81,6 +81,7 @@ struct mips_cache_ops mips_cache_ops; void mips_config_cache(struct mips_cpuinfo * cpuinfo) { + switch (cpuinfo->l1.ic_linesize) { case 16: mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16; @@ -223,7 +224,9 @@ mips_config_cache(struct mips_cpuinfo * #endif /* Check that all cache ops are set up. */ - if (mips_picache_size || 1) { /* XXX- must have primary Icache */ + /* must have primary Icache */ + if (cpuinfo->l1.ic_size) { + if (!mips_cache_ops.mco_icache_sync_all) panic("no icache_sync_all cache op"); if (!mips_cache_ops.mco_icache_sync_range) @@ -231,7 +234,8 @@ mips_config_cache(struct mips_cpuinfo * if (!mips_cache_ops.mco_icache_sync_range_index) panic("no icache_sync_range_index cache op"); } - if (mips_pdcache_size || 1) { /* XXX- must have primary Icache */ + /* must have primary Dcache */ + if (cpuinfo->l1.dc_size) { if (!mips_cache_ops.mco_pdcache_wbinv_all) panic("no pdcache_wbinv_all"); if (!mips_cache_ops.mco_pdcache_wbinv_range)