From nobody Fri Apr 7 02:59:40 2023 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Pt34d2spLz441pG for ; Fri, 7 Apr 2023 02:59:45 +0000 (UTC) (envelope-from jrtc27@jrtc27.com) Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "smtp.gmail.com", Issuer "GTS CA 1D4" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Pt34c0k92z3CwN for ; Fri, 7 Apr 2023 02:59:44 +0000 (UTC) (envelope-from jrtc27@jrtc27.com) Authentication-Results: mx1.freebsd.org; none Received: by mail-wr1-f53.google.com with SMTP id r11so41229553wrr.12 for ; Thu, 06 Apr 2023 19:59:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680836382; h=to:references:message-id:content-transfer-encoding:cc:date :in-reply-to:from:subject:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k7ugg5xGecE/rAI9SbgE6m8kIy/tN0cv/7I0AeFC/OM=; b=TE3IlQZHQiDZbflXBqxUzQCxVIwElFum2b5Vkn4TzJKjH6RsGiEAWyaFCnIRnyNPD+ 5aNOR6kNXH9fLuKoSFS1xrqvj5auMM8NUd6iAOI86FArCf11vD4pH7pbF1mhXbTZhRXz 2pv/FbMhT7lhtKprzXLQ82vNZGFakmyZB6Ju0FDJRkYfQkHLe0rnoONw89J2YbTOdHB7 PwoHFNl//xaofhk0E6edrn/7FFAmMC+08w6z5TVyLE84fHvDb9nNx2TmkiBAdaO7l/dN tucAASCUgR/8p4/4OLb2gQVNEhpHOjAH9faTFuZ6zTHBRbBDoZ2fDeyH77dY3TIWGFbo wEOA== X-Gm-Message-State: AAQBX9cx9ajRybtaSI0WrolCDi3GuCs41mXzWeBfXKBFQwVaK7NtovKn Ae9CPsCwNd1DzcPthK3i8VDf3Q== X-Google-Smtp-Source: AKy350ZQhe4Afg21Xgk1xPkEo3CJ9o3jW6JPDNcW+YFw5ZPCRhp+wYFj8mqtSIXVKd1lu2Od7Tt1cQ== X-Received: by 2002:adf:db05:0:b0:2e4:b4f8:896a with SMTP id s5-20020adfdb05000000b002e4b4f8896amr248102wri.49.1680836381647; Thu, 06 Apr 2023 19:59:41 -0700 (PDT) Received: from smtpclient.apple (global-5-142.n-2.net.cam.ac.uk. [131.111.5.142]) by smtp.gmail.com with ESMTPSA id m10-20020a5d4a0a000000b002cde626cd96sm3231088wrq.65.2023.04.06.19.59.40 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2023 19:59:41 -0700 (PDT) Content-Type: text/plain; charset=utf-8 List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-main@freebsd.org X-BeenThere: dev-commits-src-main@freebsd.org Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3696.120.41.1.1\)) Subject: Re: git: 4720afaffe7e - main - Improve RK3568 pcie phy handling codes a bit. From: Jessica Clarke In-Reply-To: <202304070255.3372tIg6078531@gitrepo.freebsd.org> Date: Fri, 7 Apr 2023 03:59:40 +0100 Cc: "src-committers@freebsd.org" , "dev-commits-src-all@freebsd.org" , "dev-commits-src-main@freebsd.org" Content-Transfer-Encoding: quoted-printable Message-Id: References: <202304070255.3372tIg6078531@gitrepo.freebsd.org> To: Ganbold Tsagaankhuu X-Mailer: Apple Mail (2.3696.120.41.1.1) X-Rspamd-Queue-Id: 4Pt34c0k92z3CwN X-Spamd-Bar: ---- X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[]; ASN(0.00)[asn:15169, ipnet:209.85.128.0/17, country:US] X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-ThisMailContainsUnwantedMimeParts: N On 7 Apr 2023, at 03:55, Ganbold Tsagaankhuu = wrote: >=20 > The branch main has been updated by ganbold: >=20 > URL: = https://cgit.FreeBSD.org/src/commit/?id=3D4720afaffe7e17e44ee0f8f3ab66da2f= d2b0d5da >=20 > commit 4720afaffe7e17e44ee0f8f3ab66da2fd2b0d5da > Author: Ganbold Tsagaankhuu > AuthorDate: 2023-04-07 02:54:13 +0000 > Commit: Ganbold Tsagaankhuu > CommitDate: 2023-04-07 02:54:13 +0000 >=20 > Improve RK3568 pcie phy handling codes a bit. >=20 > Move phy bifurcation code to a separate function > that can be called during the attach phase. > Also initialize both pcie lanes accordingly. No attempt at code review, just like all your recent commits? > --- > sys/arm64/rockchip/rk3568_pciephy.c | 87 = +++++++++++++++++++++++-------------- > 1 file changed, 55 insertions(+), 32 deletions(-) >=20 > diff --git a/sys/arm64/rockchip/rk3568_pciephy.c = b/sys/arm64/rockchip/rk3568_pciephy.c > index 5320f30e31bd..d56675521841 100644 > --- a/sys/arm64/rockchip/rk3568_pciephy.c > +++ b/sys/arm64/rockchip/rk3568_pciephy.c > @@ -56,9 +56,12 @@ > #define GRF_PCIE30PHY_CON4 0x10 > #define GRF_PCIE30PHY_CON5 0x14 > #define GRF_PCIE30PHY_CON6 0x18 > +#define GRF_BIFURCATION_LANE_1 0 > +#define GRF_BIFURCATION_LANE_2 1 > #define GRF_PCIE30PHY_WR_EN (0xf << 16) > #define GRF_PCIE30PHY_CON9 0x24 > -#define GRF_PCIE30PHY_DA_OCM ((1 << 15) | (1 << (15 + = 16))) > +#define GRF_PCIE30PHY_DA_OCM_MASK (1 << (15 + 16)) > +#define GRF_PCIE30PHY_DA_OCM ((1 << 15) | = GRF_PCIE30PHY_DA_OCM_MASK) > #define GRF_PCIE30PHY_STATUS0 0x80 > #define SRAM_INIT_DONE (1 << 14) >=20 > @@ -80,46 +83,42 @@ struct rk3568_pciephy_softc { > }; >=20 >=20 > +static void > +rk3568_pciephy_bifurcate(device_t dev, int control, uint32_t lane) > +{ > + struct rk3568_pciephy_softc *sc =3D device_get_softc(dev); > + > + switch (lane) { > + case 0: > + SYSCON_WRITE_4(sc->phy_grf, control, = GRF_PCIE30PHY_WR_EN); > + return; > + case 1: > + SYSCON_WRITE_4(sc->phy_grf, control, > + GRF_PCIE30PHY_WR_EN | GRF_BIFURCATION_LANE_1); > + break; > + case 2: > + SYSCON_WRITE_4(sc->phy_grf, control, > + GRF_PCIE30PHY_WR_EN | GRF_BIFURCATION_LANE_2); > + break; > + default: > + device_printf(dev, "Illegal lane %d\n", lane); > + return; This doesn=E2=80=99t report failure?.. > + } > + if (bootverbose) > + device_printf(dev, "lane %d @ pcie3x%d\n", lane, > + (control =3D=3D GRF_PCIE30PHY_CON5) ? 1 : 2); > +} > + > /* PHY class and methods */ > static int > rk3568_pciephy_enable(struct phynode *phynode, bool enable) > { > device_t dev =3D phynode_get_device(phynode); > struct rk3568_pciephy_softc *sc =3D device_get_softc(dev); > - uint32_t data_lanes[2] =3D { 0, 0 }; > int count; >=20 > if (enable) { > - /* Deassert PCIe PMA output clamp mode */ > - SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON9, > - GRF_PCIE30PHY_DA_OCM); > - > - /* Set bifurcation according to DT entry */ > - if (OF_hasprop(sc->node, "data-lanes")) { > - OF_getencprop(sc->node, "data-lanes", = data_lanes, > - sizeof(data_lanes)); > - if (data_lanes[0] > 0) { > - SYSCON_WRITE_4(sc->phy_grf, = GRF_PCIE30PHY_CON5, > - GRF_PCIE30PHY_WR_EN | (data_lanes[0] = - 1)); > - device_printf(dev, "pcie3x1 1 lane\n"); > - } > - if (data_lanes[1] > 0) { > - SYSCON_WRITE_4(sc->phy_grf, = GRF_PCIE30PHY_CON6, > - GRF_PCIE30PHY_WR_EN | (data_lanes[1] = - 1)); > - device_printf(dev, "pcie3x2 1 lane\n"); > - } > - if (data_lanes[0] > 1 || data_lanes[1] > 1) > - SYSCON_WRITE_4(sc->phy_grf, = GRF_PCIE30PHY_CON1, > - GRF_PCIE30PHY_DA_OCM); > - > - } else { > - SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON5, > - GRF_PCIE30PHY_WR_EN); > - SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON6, > - GRF_PCIE30PHY_WR_EN); > - device_printf(dev, "pcie3 2 lanes\n"); > - } > - > + /* Pull PHY out of reset */ > hwreset_deassert(sc->phy_reset); >=20 > /* Poll for SRAM loaded and ready */ > @@ -165,6 +164,7 @@ rk3568_pciephy_attach(device_t dev) > struct rk3568_pciephy_softc *sc =3D device_get_softc(dev); > struct phynode_init_def phy_init; > struct phynode *phynode; > + uint32_t data_lanes[2] =3D { 0, 0 }; > int rid =3D 0; >=20 > sc->dev =3D dev; > @@ -212,6 +212,29 @@ rk3568_pciephy_attach(device_t dev) >=20 > /* Set RC/EP mode not implemented yet (RC mode only) */ >=20 > + /* Set bifurcation according to "data-lanes" entry */ > + if (OF_hasprop(sc->node, "data-lanes")) { > + OF_getencprop(sc->node, "data-lanes", data_lanes, > + sizeof(data_lanes)); > + } > + else This does not conform to style(9). > + if (bootverbose) > + device_printf(dev, "lane 1 & 2 @pcie3x2\n"); These seems like messy printfs. Jess > + > + /* Deassert PCIe PMA output clamp mode */ > + SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON9, = GRF_PCIE30PHY_DA_OCM); > + > + /* Configure PHY HW accordingly */ > + rk3568_pciephy_bifurcate(dev, GRF_PCIE30PHY_CON5, = data_lanes[0]); > + rk3568_pciephy_bifurcate(dev, GRF_PCIE30PHY_CON6, = data_lanes[1]); > + > + if (data_lanes[0] || data_lanes[1]) > + SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON1, > + GRF_PCIE30PHY_DA_OCM); > + else > + SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON1, > + GRF_PCIE30PHY_DA_OCM_MASK); > + > bzero(&phy_init, sizeof(phy_init)); > phy_init.id =3D PHY_NONE; > phy_init.ofw_node =3D sc->node;