From owner-svn-src-head@FreeBSD.ORG Thu May 5 19:15:15 2011 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B5C96106566C; Thu, 5 May 2011 19:15:15 +0000 (UTC) (envelope-from delphij@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id A3FC18FC19; Thu, 5 May 2011 19:15:15 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p45JFFNB012404; Thu, 5 May 2011 19:15:15 GMT (envelope-from delphij@svn.freebsd.org) Received: (from delphij@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p45JFF12012402; Thu, 5 May 2011 19:15:15 GMT (envelope-from delphij@svn.freebsd.org) Message-Id: <201105051915.p45JFF12012402@svn.freebsd.org> From: Xin LI Date: Thu, 5 May 2011 19:15:15 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r221509 - head/sys/dev/coretemp X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 May 2011 19:15:15 -0000 Author: delphij Date: Thu May 5 19:15:15 2011 New Revision: 221509 URL: http://svn.freebsd.org/changeset/base/221509 Log: Detect and set Atom's Tj(max) to 90 if it's not the 45nm D400/D500/N400 series. MFC after: 2 weeks Modified: head/sys/dev/coretemp/coretemp.c Modified: head/sys/dev/coretemp/coretemp.c ============================================================================== --- head/sys/dev/coretemp/coretemp.c Thu May 5 18:56:48 2011 (r221508) +++ head/sys/dev/coretemp/coretemp.c Thu May 5 19:15:15 2011 (r221509) @@ -197,6 +197,15 @@ coretemp_attach(device_t dev) default: /* Unknown stepping */ break; } + } else if (cpu_model == 0x1c) { + switch (cpu_stepping) { + case 0xa: /* 45nm Atom D400, N400 and D500 series */ + sc->sc_tjmax = 100; + break; + default: + sc->sc_tjmax = 90; + break; + } } else { /* * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.