From owner-svn-src-stable@FreeBSD.ORG Fri Jul 26 06:28:42 2013 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 947957B4; Fri, 26 Jul 2013 06:28:42 +0000 (UTC) (envelope-from hselasky@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 676702742; Fri, 26 Jul 2013 06:28:42 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r6Q6SgnD010421; Fri, 26 Jul 2013 06:28:42 GMT (envelope-from hselasky@svn.freebsd.org) Received: (from hselasky@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r6Q6SgkY010420; Fri, 26 Jul 2013 06:28:42 GMT (envelope-from hselasky@svn.freebsd.org) Message-Id: <201307260628.r6Q6SgkY010420@svn.freebsd.org> From: Hans Petter Selasky Date: Fri, 26 Jul 2013 06:28:42 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org Subject: svn commit: r253666 - stable/8/sys/dev/usb/controller X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Jul 2013 06:28:42 -0000 Author: hselasky Date: Fri Jul 26 06:28:41 2013 New Revision: 253666 URL: http://svnweb.freebsd.org/changeset/base/253666 Log: MFC r253532: Fix an XHCI regression: The Block Event Interrupts, BEI, feature does not work like expected with the Renesas XHCI chipsets. Revert feature. While at it correct the TD SIZE computation in case of Zero Length Packet, ZLP, in the end of a multi frame USB transfer. PR: usb/180726 Modified: stable/8/sys/dev/usb/controller/xhci.c Directory Properties: stable/8/sys/ (props changed) stable/8/sys/dev/ (props changed) stable/8/sys/dev/usb/ (props changed) Modified: stable/8/sys/dev/usb/controller/xhci.c ============================================================================== --- stable/8/sys/dev/usb/controller/xhci.c Fri Jul 26 06:24:33 2013 (r253665) +++ stable/8/sys/dev/usb/controller/xhci.c Fri Jul 26 06:28:41 2013 (r253666) @@ -1654,7 +1654,6 @@ restart: /* fill out buffer pointers */ if (average == 0) { - npkt = 0; memset(&buf_res, 0, sizeof(buf_res)); } else { usbd_get_page(temp->pc, temp->offset + @@ -1669,15 +1668,17 @@ restart: buf_res.length = XHCI_TD_PAGE_SIZE; npkt_off += buf_res.length; - - /* setup npkt */ - npkt = (len_old - npkt_off + temp->max_packet_size - 1) / - temp->max_packet_size; - - if (npkt > 31) - npkt = 31; } + /* setup npkt */ + npkt = (len_old - npkt_off + temp->max_packet_size - 1) / + temp->max_packet_size; + + if (npkt == 0) + npkt = 1; + else if (npkt > 31) + npkt = 31; + /* fill out TRB's */ td->td_trb[x].qwTrb0 = htole64((uint64_t)buf_res.physaddr); @@ -1691,9 +1692,7 @@ restart: switch (temp->trb_type) { case XHCI_TRB_TYPE_ISOCH: - /* BEI: Interrupts are inhibited until EOT */ dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | - XHCI_TRB_3_BEI_BIT | XHCI_TRB_3_TBC_SET(temp->tbc) | XHCI_TRB_3_TLBPC_SET(temp->tlbpc); if (td != td_first) { @@ -1728,10 +1727,8 @@ restart: dword |= XHCI_TRB_3_DIR_IN; break; default: /* XHCI_TRB_TYPE_NORMAL */ - /* BEI: Interrupts are inhibited until EOT */ dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | - XHCI_TRB_3_BEI_BIT | XHCI_TRB_3_TBC_SET(temp->tbc) | XHCI_TRB_3_TLBPC_SET(temp->tlbpc); if (temp->direction == UE_DIR_IN) @@ -1810,6 +1807,7 @@ restart: usb_pc_cpu_flush(td_first->page_cache); } + /* clear TD SIZE to zero, hence this is the last TRB */ /* remove chain bit because this is the last TRB in the chain */ td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);