From owner-svn-src-all@freebsd.org Thu Oct 27 21:31:58 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 4B2ADC2483D; Thu, 27 Oct 2016 21:31:58 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id F2A8CDC1; Thu, 27 Oct 2016 21:31:57 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u9RLVvUb082464; Thu, 27 Oct 2016 21:31:57 GMT (envelope-from jhb@FreeBSD.org) Received: (from jhb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u9RLVvJZ082463; Thu, 27 Oct 2016 21:31:57 GMT (envelope-from jhb@FreeBSD.org) Message-Id: <201610272131.u9RLVvJZ082463@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhb set sender to jhb@FreeBSD.org using -f From: John Baldwin Date: Thu, 27 Oct 2016 21:31:57 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r308005 - head/sys/x86/cpufreq X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Oct 2016 21:31:58 -0000 Author: jhb Date: Thu Oct 27 21:31:56 2016 New Revision: 308005 URL: https://svnweb.freebsd.org/changeset/base/308005 Log: Add powerd(8) support for several families of AMD CPUs. Use the same logic to calculate the nominal CPU frequency from the P-state MSRs on family 0x12, 0x15, and 0x16 CPUs as is used for family 0x10. Family 0x14 was included in the original patch in the PR but I left that out as the BIOS writer's guide for family 0x14 CPUs show a different layout for the relevant MSR and include a different formulate for calculating the frequency. While here, simplify a few expressions and print out the family of unsupported CPUs in hex rather than decimal. PR: 212020 Submitted by: Anthony Jenkins MFC after: 1 month Differential Revision: https://reviews.freebsd.org/D7587 Modified: head/sys/x86/cpufreq/hwpstate.c Modified: head/sys/x86/cpufreq/hwpstate.c ============================================================================== --- head/sys/x86/cpufreq/hwpstate.c Thu Oct 27 21:23:14 2016 (r308004) +++ head/sys/x86/cpufreq/hwpstate.c Thu Oct 27 21:31:56 2016 (r308005) @@ -408,25 +408,27 @@ hwpstate_get_info_from_msr(device_t dev) hwpstate_set = sc->hwpstate_settings; for (i = 0; i < sc->cfnum; i++) { msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i); - if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) { + if ((msr & ((uint64_t)1 << 63)) == 0) { HWPSTATE_DEBUG(dev, "msr is not valid.\n"); return (ENXIO); } did = AMD_10H_11H_CUR_DID(msr); fid = AMD_10H_11H_CUR_FID(msr); + + /* Convert fid/did to frequency. */ switch(family) { case 0x11: - /* fid/did to frequency */ - hwpstate_set[i].freq = 100 * (fid + 0x08) / (1 << did); + hwpstate_set[i].freq = (100 * (fid + 0x08)) >> did; break; case 0x10: - /* fid/did to frequency */ - hwpstate_set[i].freq = 100 * (fid + 0x10) / (1 << did); + case 0x12: + case 0x15: + case 0x16: + hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did; break; default: - HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family %d CPU's are not implemented yet. sorry.\n", family); + HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family 0x%02x CPU's are not implemented yet. sorry.\n", family); return (ENXIO); - break; } hwpstate_set[i].pstate_id = i; /* There was volts calculation, but deleted it. */