From owner-svn-src-head@freebsd.org Sat May 5 05:22:12 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6AA89FCA7F1; Sat, 5 May 2018 05:22:12 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 1E8607D80D; Sat, 5 May 2018 05:22:12 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 000F41969C; Sat, 5 May 2018 05:22:11 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w455MBAo093860; Sat, 5 May 2018 05:22:11 GMT (envelope-from avg@FreeBSD.org) Received: (from avg@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w455MBKa093858; Sat, 5 May 2018 05:22:11 GMT (envelope-from avg@FreeBSD.org) Message-Id: <201805050522.w455MBKa093858@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: avg set sender to avg@FreeBSD.org using -f From: Andriy Gapon Date: Sat, 5 May 2018 05:22:11 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r333269 - head/sys/dev/amdsbwd X-SVN-Group: head X-SVN-Commit-Author: avg X-SVN-Commit-Paths: head/sys/dev/amdsbwd X-SVN-Commit-Revision: 333269 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 May 2018 05:22:12 -0000 Author: avg Date: Sat May 5 05:22:11 2018 New Revision: 333269 URL: https://svnweb.freebsd.org/changeset/base/333269 Log: amdsbwd: fix reboot status reporting Originally, I overlooked that PMIO register 0xc0 has a dual personality. It can either be S5/Reset Status register or Misc. Fix register (aka debug status register). The mode is controlled by bit 2 in PMIO register 0xc4. Apparently there are register programming requirements for the second personality, so many BIOSes leave the register, after programming it, in that mode. So, we need to switch the register to the correct mode. Additionally, AMDSB8_WD_RST_STS was defined incorrectly as bit 13 while it is actually bit 25 (and the register's width is 32 bits, not 16). With this change I see the following in dmesg after a reset by the watchdog: amdsbwd0: ResetStatus = 0x42000000 amdsbwd0: Previous Reset was caused by Watchdog MFC after: 2 weeks Modified: head/sys/dev/amdsbwd/amd_chipset.h head/sys/dev/amdsbwd/amdsbwd.c Modified: head/sys/dev/amdsbwd/amd_chipset.h ============================================================================== --- head/sys/dev/amdsbwd/amd_chipset.h Sat May 5 05:19:32 2018 (r333268) +++ head/sys/dev/amdsbwd/amd_chipset.h Sat May 5 05:22:11 2018 (r333269) @@ -95,9 +95,10 @@ #define AMDSB8_WDT_32KHZ 0x00 #define AMDSB8_WDT_1HZ 0x03 #define AMDSB8_WDT_RES_MASK 0x03 -#define AMDSB8_PM_RESET_STATUS0 0xc0 -#define AMDSB8_PM_RESET_STATUS1 0xc1 -#define AMDSB8_WD_RST_STS 0x20 +#define AMDSB8_PM_RESET_STATUS 0xc0 /* 32 bit wide */ +#define AMDSB8_WD_RST_STS 0x2000000 +#define AMDSB8_PM_RESET_CTRL 0xc4 +#define AMDSB8_RST_STS_DIS 0x04 /* * Newer FCH registers in the PMIO space. Modified: head/sys/dev/amdsbwd/amdsbwd.c ============================================================================== --- head/sys/dev/amdsbwd/amdsbwd.c Sat May 5 05:19:32 2018 (r333268) +++ head/sys/dev/amdsbwd/amdsbwd.c Sat May 5 05:22:11 2018 (r333269) @@ -321,16 +321,23 @@ amdsbwd_probe_sb7xx(device_t dev, struct resource *pmr static void amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) { - uint8_t val; - int i; + uint32_t val; + int i; /* Report cause of previous reset for user's convenience. */ - val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0); + + val = pmio_read(pmres, AMDSB8_PM_RESET_CTRL); + if ((val & AMDSB8_RST_STS_DIS) != 0) { + val &= ~AMDSB8_RST_STS_DIS; + pmio_write(pmres, AMDSB8_PM_RESET_CTRL, val); + } + val = 0; + for (i = 3; i >= 0; i--) { + val <<= 8; + val |= pmio_read(pmres, AMDSB8_PM_RESET_STATUS + i); + } if (val != 0) - amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); - val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1); - if (val != 0) - amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); + amdsbwd_verbose_printf(dev, "ResetStatus = 0x%08x\n", val); if ((val & AMDSB8_WD_RST_STS) != 0) device_printf(dev, "Previous Reset was caused by Watchdog\n");