From owner-svn-src-head@freebsd.org Fri Oct 25 14:46:10 2019 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 0DA95172846; Fri, 25 Oct 2019 14:46:10 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4706PF6SSsz4bHJ; Fri, 25 Oct 2019 14:46:09 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id C23E427E74; Fri, 25 Oct 2019 14:46:09 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x9PEk9ie098952; Fri, 25 Oct 2019 14:46:09 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x9PEk9mX098951; Fri, 25 Oct 2019 14:46:09 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201910251446.x9PEk9mX098951@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Fri, 25 Oct 2019 14:46:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r354072 - head/sys/arm64/include X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: head/sys/arm64/include X-SVN-Commit-Revision: 354072 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Oct 2019 14:46:10 -0000 Author: andrew Date: Fri Oct 25 14:46:09 2019 New Revision: 354072 URL: https://svnweb.freebsd.org/changeset/base/354072 Log: Remove the arm4 ID register masks, they are not needed after r353641. Sponsored by: DARPA, AFRL Modified: head/sys/arm64/include/armreg.h Modified: head/sys/arm64/include/armreg.h ============================================================================== --- head/sys/arm64/include/armreg.h Fri Oct 25 14:33:07 2019 (r354071) +++ head/sys/arm64/include/armreg.h Fri Oct 25 14:46:09 2019 (r354072) @@ -176,7 +176,6 @@ #define ICC_SRE_EL2_EN (1U << 3) /* ID_AA64DFR0_EL1 */ -#define ID_AA64DFR0_MASK UL(0x0000000ff0f0ffff) #define ID_AA64DFR0_DebugVer_SHIFT 0 #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) #define ID_AA64DFR0_DebugVer(x) ((x) & ID_AA64DFR0_DebugVer_MASK) @@ -214,7 +213,6 @@ #define ID_AA64DFR0_PMSVer_V1 (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) /* ID_AA64ISAR0_EL1 */ -#define ID_AA64ISAR0_MASK UL(0x0000fffff0fffff0) #define ID_AA64ISAR0_AES_SHIFT 4 #define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) #define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) @@ -269,7 +267,6 @@ #define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) /* ID_AA64ISAR1_EL1 */ -#define ID_AA64ISAR1_MASK UL(0x00000000ffffffff) #define ID_AA64ISAR1_DPB_SHIFT 0 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) #define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) @@ -312,7 +309,6 @@ #define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) /* ID_AA64MMFR0_EL1 */ -#define ID_AA64MMFR0_MASK UL(0x00000000ffffffff) #define ID_AA64MMFR0_PARange_SHIFT 0 #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) #define ID_AA64MMFR0_PARange(x) ((x) & ID_AA64MMFR0_PARange_MASK) @@ -360,7 +356,6 @@ #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) /* ID_AA64MMFR1_EL1 */ -#define ID_AA64MMFR1_MASK UL(0x00000000ffffffff) #define ID_AA64MMFR1_HAFDBS_SHIFT 0 #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) #define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) @@ -407,7 +402,6 @@ /* ID_AA64MMFR2_EL1 */ #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 -#define ID_AA64MMFR2_MASK UL(0x000000000fffffff) #define ID_AA64MMFR2_CnP_SHIFT 0 #define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) #define ID_AA64MMFR2_CnP(x) ((x) & ID_AA64MMFR2_CnP_MASK) @@ -445,7 +439,6 @@ #define ID_AA64MMFR2_NV_IMPL (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) /* ID_AA64PFR0_EL1 */ -#define ID_AA64PFR0_MASK UL(0x0000000fffffffff) #define ID_AA64PFR0_EL0_SHIFT 0 #define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) #define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK)