From owner-freebsd-arm@FreeBSD.ORG Wed Dec 30 14:32:26 2009 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 91D6B1065670 for ; Wed, 30 Dec 2009 14:32:26 +0000 (UTC) (envelope-from tinguely@casselton.net) Received: from casselton.net (casselton.net [63.165.140.2]) by mx1.freebsd.org (Postfix) with ESMTP id 500718FC0A for ; Wed, 30 Dec 2009 14:32:26 +0000 (UTC) Received: from casselton.net (localhost [127.0.0.1]) by casselton.net (8.14.3/8.14.3) with ESMTP id nBUEWPoO021255 for ; Wed, 30 Dec 2009 08:32:25 -0600 (CST) (envelope-from tinguely@casselton.net) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=casselton.net; s=ccnMail; t=1262183545; bh=U5ZVRw5CqfskK4OcWBk2eHaZXVOJUDZ7oGwGJrrOF4k=; h=Date:From:Message-Id:To:Subject:In-Reply-To; b=WCxI3bx82soJQXXFwtkF0Kq9DpOgboWFbXWcH45q80FJMRbJ4ogJWoxeI/7hKNs93 ikQoDydcVg+ZL+6qcBPyY59IWCTnD28ftVJSvTpGTLUxLRd8t1sbCT6yhu7uqt47fY ww8nqBSebcxfhBoJEGfcPhdZ618VPVojcrXnSBMM= Received: (from tinguely@localhost) by casselton.net (8.14.3/8.14.2/Submit) id nBUEWPVu021254 for freebsd-arm@freebsd.org; Wed, 30 Dec 2009 08:32:25 -0600 (CST) (envelope-from tinguely) Date: Wed, 30 Dec 2009 08:32:25 -0600 (CST) From: Mark Tinguely Message-Id: <200912301432.nBUEWPVu021254@casselton.net> To: freebsd-arm@freebsd.org In-Reply-To: <200912292046.nBTKknjI076659@casselton.net> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.3.2 (casselton.net [127.0.0.1]); Wed, 30 Dec 2009 08:32:25 -0600 (CST) Subject: Re: cpu_throw()/cpu_switch() and L2 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Dec 2009 14:32:26 -0000 > FYI esp Sheeva users with corruption issues: > > I was looking at my new swtch.S routine and noticed that cpu_throw() > and cpu_switch() do not wbinv the level 2 cache. For the majority of > the ARMv5 processors this does not do anything. This could effect the > Sheeva. Looking at the Sheeva "setttb" routine, wbinv both level 1 and > level 2 caches, which it needs to to if the level 2 cache is virtually > indexed. Sorry, it was purposely removed in Oct 2008 with Revision 18395. --Mark.