From owner-svn-src-all@FreeBSD.ORG Thu Feb 26 01:53:25 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id BDF71600; Thu, 26 Feb 2015 01:53:25 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 8ECE821C; Thu, 26 Feb 2015 01:53:25 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t1Q1rPfl068661; Thu, 26 Feb 2015 01:53:25 GMT (envelope-from jchandra@FreeBSD.org) Received: (from jchandra@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t1Q1rOms068658; Thu, 26 Feb 2015 01:53:24 GMT (envelope-from jchandra@FreeBSD.org) Message-Id: <201502260153.t1Q1rOms068658@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: jchandra set sender to jchandra@FreeBSD.org using -f From: "Jayachandran C." Date: Thu, 26 Feb 2015 01:53:24 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279304 - in head/sys/mips/nlm: . hal X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Feb 2015 01:53:25 -0000 Author: jchandra Date: Thu Feb 26 01:53:24 2015 New Revision: 279304 URL: https://svnweb.freebsd.org/changeset/base/279304 Log: Fix up interrupt definitions for Broadcom XLP Gather all the IRQ definitions to interrupt.h. Earlier these were in xlp.h and pic.h. Update the definition of XLP_IRQ_IS_PICINTR to check for last irq as well. Modified: head/sys/mips/nlm/hal/pic.h head/sys/mips/nlm/interrupt.h head/sys/mips/nlm/xlp.h Modified: head/sys/mips/nlm/hal/pic.h ============================================================================== --- head/sys/mips/nlm/hal/pic.h Wed Feb 25 22:41:27 2015 (r279303) +++ head/sys/mips/nlm/hal/pic.h Thu Feb 26 01:53:24 2015 (r279304) @@ -168,14 +168,9 @@ #define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX) #define PIC_CLOCK_TIMER 7 -#define PIC_IRQ_BASE 8 #if !defined(LOCORE) && !defined(__ASSEMBLY__) -#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE) -#define PIC_IRT_LAST_IRQ 63 -#define XLP_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRT_FIRST_IRQ) - /* * Misc */ Modified: head/sys/mips/nlm/interrupt.h ============================================================================== --- head/sys/mips/nlm/interrupt.h Wed Feb 25 22:41:27 2015 (r279303) +++ head/sys/mips/nlm/interrupt.h Thu Feb 26 01:53:24 2015 (r279304) @@ -34,9 +34,22 @@ /* Defines for the IRQ numbers */ -#define IRQ_IPI 41 /* 8-39 are mapped by PIC intr 0-31 */ -#define IRQ_MSGRING 6 -#define IRQ_TIMER 7 +#define IRQ_IPI 41 /* 8-39 are used by PIC interrupts */ +#define IRQ_MSGRING 6 +#define IRQ_TIMER 7 + +#define PIC_IRQ_BASE 8 +#define PIC_IRT_LAST_IRQ 39 +#define XLP_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE && \ + (irq) <= PIC_IRT_LAST_IRQ) + +#define PIC_UART_0_IRQ 9 +#define PIC_PCIE_0_IRQ 11 +#define PIC_PCIE_1_IRQ 12 +#define PIC_PCIE_2_IRQ 13 +#define PIC_PCIE_3_IRQ 14 +#define PIC_EHCI_0_IRQ 16 +#define PIC_MMC_IRQ 21 /* * XLR needs custom pre and post handlers for PCI/PCI-e interrupts Modified: head/sys/mips/nlm/xlp.h ============================================================================== --- head/sys/mips/nlm/xlp.h Wed Feb 25 22:41:27 2015 (r279303) +++ head/sys/mips/nlm/xlp.h Thu Feb 26 01:53:24 2015 (r279304) @@ -34,18 +34,6 @@ #include #include -#define PIC_UART_0_IRQ 9 - -#define PIC_PCIE_0_IRQ 11 -#define PIC_PCIE_1_IRQ 12 -#define PIC_PCIE_2_IRQ 13 -#define PIC_PCIE_3_IRQ 14 - -#define PIC_EHCI_0_IRQ 16 -#define PIC_MMC_IRQ 21 -/* 41 used by IRQ_SMP */ - - /* XLP 8xx/4xx A0, A1, A2 CPU COP0 PRIDs */ #define CHIP_PROCESSOR_ID_XLP_8XX 0x10 #define CHIP_PROCESSOR_ID_XLP_3XX 0x11