From owner-svn-src-stable-7@FreeBSD.ORG Thu Apr 15 19:22:55 2010 Return-Path: Delivered-To: svn-src-stable-7@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8FB031065687; Thu, 15 Apr 2010 19:22:55 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 7DB328FC19; Thu, 15 Apr 2010 19:22:55 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o3FJMtpQ094513; Thu, 15 Apr 2010 19:22:55 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o3FJMtwU094509; Thu, 15 Apr 2010 19:22:55 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201004151922.o3FJMtwU094509@svn.freebsd.org> From: Pyun YongHyeon Date: Thu, 15 Apr 2010 19:22:55 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org X-SVN-Group: stable-7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r206679 - stable/7/sys/dev/mii X-BeenThere: svn-src-stable-7@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 7-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Apr 2010 19:22:55 -0000 Author: yongari Date: Thu Apr 15 19:22:55 2010 New Revision: 206679 URL: http://svn.freebsd.org/changeset/base/206679 Log: MFC r205299: - Added support for 5709S/5716S PHYs. Submitted by: pyunyh PR: kern/134658, kern/136417, kern/139761, kern/140970 Modified: stable/7/sys/dev/mii/brgphy.c stable/7/sys/dev/mii/brgphyreg.h stable/7/sys/dev/mii/miidevs Directory Properties: stable/7/sys/ (props changed) stable/7/sys/cddl/contrib/opensolaris/ (props changed) stable/7/sys/contrib/dev/acpica/ (props changed) stable/7/sys/contrib/pf/ (props changed) Modified: stable/7/sys/dev/mii/brgphy.c ============================================================================== --- stable/7/sys/dev/mii/brgphy.c Thu Apr 15 19:19:59 2010 (r206678) +++ stable/7/sys/dev/mii/brgphy.c Thu Apr 15 19:22:55 2010 (r206679) @@ -75,6 +75,7 @@ struct brgphy_softc { #define BRGPHY_5706S 0x0001 #define BRGPHY_5708S 0x0002 #define BRGPHY_NOANWAIT 0x0004 +#define BRGPHY_5709S 0x0008 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ }; @@ -139,6 +140,7 @@ static const struct mii_phydesc brgphys[ MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784), MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S), MII_PHY_DESC(BROADCOM2, BCM5906), MII_PHY_END }; @@ -216,30 +218,34 @@ brgphy_attach(device_t dev) break; case MII_OUI_xxBROADCOM: switch (bsc->mii_model) { - case MII_MODEL_xxBROADCOM_BCM5706: - case MII_MODEL_xxBROADCOM_BCM5714: - /* - * The 5464 PHY used in the 5706 supports both copper - * and fiber interfaces over GMII. Need to check the - * shadow registers to see which mode is actually - * in effect, and therefore whether we have 5706C or - * 5706S. - */ - PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, - BRGPHY_SHADOW_1C_MODE_CTRL); - if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & - BRGPHY_SHADOW_1C_ENA_1000X) { - bsc->serdes_flags |= BRGPHY_5706S; - sc->mii_flags |= MIIF_HAVEFIBER; - } - break; + case MII_MODEL_xxBROADCOM_BCM5706: + case MII_MODEL_xxBROADCOM_BCM5714: + /* + * The 5464 PHY used in the 5706 supports both copper + * and fiber interfaces over GMII. Need to check the + * shadow registers to see which mode is actually + * in effect, and therefore whether we have 5706C or + * 5706S. + */ + PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, + BRGPHY_SHADOW_1C_MODE_CTRL); + if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & + BRGPHY_SHADOW_1C_ENA_1000X) { + bsc->serdes_flags |= BRGPHY_5706S; + sc->mii_flags |= MIIF_HAVEFIBER; + } + break; } break; case MII_OUI_xxBROADCOM_ALT1: switch (bsc->mii_model) { - case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: - bsc->serdes_flags |= BRGPHY_5708S; - sc->mii_flags |= MIIF_HAVEFIBER; - break; + case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: + bsc->serdes_flags |= BRGPHY_5708S; + sc->mii_flags |= MIIF_HAVEFIBER; + break; + case MII_MODEL_xxBROADCOM_ALT1_BCM5709S: + bsc->serdes_flags |= BRGPHY_5709S; + sc->mii_flags |= MIIF_HAVEFIBER; + break; } break; default: device_printf(dev, "Unrecognized OUI for PHY!\n"); @@ -619,6 +625,7 @@ brgphy_status(struct mii_softc *sc) PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); + /* Check for MRBE auto-negotiated speed results. */ switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: mii->mii_media_active |= IFM_10_FL; break; @@ -630,11 +637,40 @@ brgphy_status(struct mii_softc *sc) mii->mii_media_active |= IFM_2500_SX; break; } + /* Check for MRBE auto-negotiated duplex results. */ if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) mii->mii_media_active |= IFM_FDX; else mii->mii_media_active |= IFM_HDX; - } + + } else if (bsc->serdes_flags & BRGPHY_5709S) { + + /* Select GP Status Block of the AN MMD, get autoneg results. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); + xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); + + /* Restore IEEE0 block (assumed in all brgphy(4) code). */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); + + /* Check for MRBE auto-negotiated speed results. */ + switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { + case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: + mii->mii_media_active |= IFM_10_FL; break; + case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: + mii->mii_media_active |= IFM_100_FX; break; + case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: + mii->mii_media_active |= IFM_1000_SX; break; + case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: + mii->mii_media_active |= IFM_2500_SX; break; + } + + /* Check for MRBE auto-negotiated duplex results. */ + if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; + } + } #if 0 @@ -955,6 +991,7 @@ brgphy_reset(struct mii_softc *sc) struct bge_softc *bge_sc = NULL; struct bce_softc *bce_sc = NULL; struct ifnet *ifp; + int val; /* Perform a standard PHY reset. */ mii_phy_reset(sc); @@ -1077,7 +1114,49 @@ brgphy_reset(struct mii_softc *sc) PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); } - } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { + } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && + (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { + + /* Select the SerDes Digital block of the AN MMD. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); + val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); + val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; + val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; + PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); + + /* Select the Over 1G block of the AN MMD. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); + + /* Enable autoneg "Next Page" to advertise 2.5G support. */ + val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); + if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) + val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; + else + val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; + PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); + + /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); + + /* Enable MRBE speed autoneg. */ + val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); + val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | + BRGPHY_MRBE_MSG_PG5_NP_T2; + PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); + + /* Select the Clause 73 User B0 block of the AN MMD. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); + + /* Enable MRBE speed autoneg. */ + PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, + BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | + BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | + BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); + + /* Restore IEEE0 block (assumed in all brgphy(4) code). */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); + + } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) brgphy_fixup_disable_early_dac(sc); Modified: stable/7/sys/dev/mii/brgphyreg.h ============================================================================== --- stable/7/sys/dev/mii/brgphyreg.h Thu Apr 15 19:19:59 2010 (r206678) +++ stable/7/sys/dev/mii/brgphyreg.h Thu Apr 15 19:22:55 2010 (r206679) @@ -359,6 +359,61 @@ /* End: PHY register values for the 5708S SerDes PHY */ /*******************************************************/ +/*******************************************************/ +/* Begin: PHY register values for the 5709S SerDes PHY */ +/*******************************************************/ + +/* 5709S SerDes "General Purpose Status" Registers */ +#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 +#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 +#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 +#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 +#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 + +/* 5709S SerDes "SerDes Digital" Registers */ +#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 +#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 +#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 +#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 + +/* 5709S SerDes "Over 1G" Registers */ +#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 +#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 + +/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ +#define BRGPHY_BLOCK_ADDR_MRBE 0x8350 +#define BRGPHY_MRBE_MSG_PG5_NP 0x10 +#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 +#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0001 + +/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ +#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 +#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 +#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 +#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 +#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 + +/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ +#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 + +/* 5709S SerDes "Combo IEEE 0" Registers */ +#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 + +#define BRGPHY_ADDR_EXT 0x1E +#define BRGPHY_BLOCK_ADDR 0x1F + +#define BRGPHY_ADDR_EXT_AN_MMD 0x3800 + +/*******************************************************/ +/* End: PHY register values for the 5709S SerDes PHY */ +/*******************************************************/ + #define BRGPHY_INTRS \ ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) Modified: stable/7/sys/dev/mii/miidevs ============================================================================== --- stable/7/sys/dev/mii/miidevs Thu Apr 15 19:19:59 2010 (r206678) +++ stable/7/sys/dev/mii/miidevs Thu Apr 15 19:22:55 2010 (r206679) @@ -152,6 +152,7 @@ model xxBROADCOM_ALT1 BCM5722 0x002d BCM model xxBROADCOM_ALT1 BCM5784 0x003a BCM5784 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5709C 0x003c BCM5709C 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5761 0x003d BCM5761 10/100/1000baseTX PHY +model xxBROADCOM_ALT1 BCM5709S 0x003f BCM5709S 1000/2500baseSX PHY model BROADCOM2 BCM5906 0x0004 BCM5906 10/100baseTX PHY /* Cicada Semiconductor PHYs (now owned by Vitesse?) */