Date: Tue, 20 Apr 2010 19:53:23 +0530 From: "C. Jayachandran" <c.jayachandran@gmail.com> To: Rui Paulo <rpaulo@freebsd.org> Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] Account RMI XLR interrupts Message-ID: <y2o98a59be81004200723zbab2a5a5y1556b8106a3195f6@mail.gmail.com> In-Reply-To: <g2u98a59be81004200718md331d3b1g5bff1c764b58fc73@mail.gmail.com> References: <BAAA25BC-6094-4B5B-9C83-A330933EBA51@freebsd.org> <g2u98a59be81004200718md331d3b1g5bff1c764b58fc73@mail.gmail.com>
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Please ignore the first part of the mail about array size, I seem to
have missed the definition in rmi files.
JC.
On Tue, Apr 20, 2010 at 7:48 PM, C. Jayachandran
<c.jayachandran@gmail.com> wrote:
> On Tue, Apr 20, 2010 at 5:06 PM, Rui Paulo <rpaulo@freebsd.org> wrote:
>> Hi,
>> The following patch accounts interrupts on the XLR and makes vmstat -i a=
nd systat work display useful data. I think the commented out atomic inc ca=
n go away, but I'm not sure.
>>
>> Here's an example:
>>
>> $ vmstat -i
>> interrupt =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0total =A0 =
=A0 =A0 rate
>> int16: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 56118 =A0=
=A0 =A0 =A0984
>> int17: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 214 =
=A0 =A0 =A0 =A0 =A03
>> Total =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A056332 =
=A0 =A0 =A0 =A0988
>>
>> int16 is the timer and int17 is the network interface (rge1).
>
> Are you sure that the mips_intr_events array has the size to hold all
> the XLR interrupts? =A0The XLR has a slightly different scheme (with
> COP0 EIRR EIMR registers) and can have upto 64 interrupts.
>
> A mechanism to unify the interrupt, and handling the XLR PIC may be a goo=
d idea.
>
> The network packets come on MSGRING interrupt - only link status etc
> will come on the GMAC interrupt.
>
> JC.
>
>
>> Index: intr_machdep.c
>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>> --- intr_machdep.c =A0 =A0 =A0(revision 206791)
>> +++ intr_machdep.c =A0 =A0 =A0(working copy)
>> @@ -157,28 +157,17 @@
>> =A0 =A0 =A0 =A0for (i =3D sizeof(eirr) * 8 - 1; i >=3D 0; i--) {
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if ((eirr & (1ULL << i)) =3D=3D 0)
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0continue;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ie =3D mips_intr_events[i];
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* atomic_add_long(mih->cntp, 1); */
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Don't account special IRQs */
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 switch (i) {
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 case IRQ_IPI:
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 case IRQ_MSGRING:
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 default:
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mips_intrcnt_inc(mips_intr=
_counters[i]);
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
>>
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0write_c0_eirr64(1ULL << i);
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pic_ack(i, 0);
>>
>> Regards,
>> --
>> Rui Paulo
>
--=20
C. Jayachandran c.jayachandran@gmail.com
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