From owner-freebsd-arm@FreeBSD.ORG Tue Mar 11 01:24:29 2014 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 5F652C08 for ; Tue, 11 Mar 2014 01:24:29 +0000 (UTC) Received: from mail-ig0-x229.google.com (mail-ig0-x229.google.com [IPv6:2607:f8b0:4001:c05::229]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 300ABB71 for ; Tue, 11 Mar 2014 01:24:29 +0000 (UTC) Received: by mail-ig0-f169.google.com with SMTP id h18so10236525igc.0 for ; Mon, 10 Mar 2014 18:24:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=Ith902wSA2A4jCBtZo8YKCrlOEqXdzH/ow2Qg63QrMc=; b=DJsn78ZOLfktJwKApTOHl1OsUEUw4uKuA2ZrAcI65GT4wh9TJoamZ5OqQp4Oy7JZmq VRnwvi8DwV3/5N2D5eU2pAh0CKbDoRRoU5hGic72CNy3awDj3U6QaEnGsBh5MoMpO+ED uLHy4BizZi3gMR1XX5XlwVMInP1aRv6SBGfpnHlrK6QGlQGzupTDp2mrWYvPlAC6BLpd crtQlbMeVUPQmNMVpF3ZmTIM5Zwa5HZGezFJCpL1LWe1cd/Htf1nTowvDJvskVpNkuWq fB9sH9jdEb0y1WfzeeDozU5YN8tDScd8wFqd7DP1usRbqf014Upy35RFWxg1fnbnt/9P JY3w== MIME-Version: 1.0 X-Received: by 10.50.25.138 with SMTP id c10mr16515989igg.15.1394501068598; Mon, 10 Mar 2014 18:24:28 -0700 (PDT) Received: by 10.64.107.3 with HTTP; Mon, 10 Mar 2014 18:24:28 -0700 (PDT) Date: Tue, 11 Mar 2014 09:24:28 +0800 Message-ID: Subject: Enabling second core on A20 (Dual core Cortex A7) From: Ganbold Tsagaankhuu To: "freebsd-arm@freebsd.org" Content-Type: text/plain; charset=ISO-8859-1 X-Content-Filtered-By: Mailman/MimeDel 2.1.17 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Mar 2014 01:24:29 -0000 Hi, I'm trying to enable SMP on cubieboard2 which has A20 SoC, dual core Cortex A7. However it boots with "WARNING: Some AP's failed to start" msg. The code is at: https://github.com/tsgan/allwinner_a10/blob/master/a20/a20_mp.c Linux code is at: https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/arch/arm/mach-sun7i/platsmp.c https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/arch/arm/mach-sun7i/headsmp.S My asm foo is not good so I thought I'd better ask if it could be related to locore.S or early initialization codes for enabling SMP. ARM Cortex A7 MPCore Tech ref manual says (page 40): "To power up the processor, apply the following sequence: 1. Assert nCOREPORESET LOW and hold L1RSTDISABLE LOW. Ensure DBGPWRDUP is held LOW to prevent any external debug access to the processor. 2. Apply power to the Vcore power domain. Keep the state of the signals nCOREPORESET, L1RSTDISABLE and DBGPWRDUP LOW. 3. When the power domain has stabilized and reset has been asserted for four or more cycles, release the processor output clamps. 4. De-assert resets. 5. Assert DBGPWRDUP HIGH to allow external debug access to the processor. 6. If required use software to restore the state of the processor prior to power-down. 7. Assert ACTLR.SMP bit HIGH for SMP mode. Continue a normal power-on reset sequence." It seems setting ACTLR smp bit is taken place in cortexa_setup() of cpufunc.c which seems to be called before platform_mp_start_ap(). But I maybe overlooked this, or the problem could be somewhere else, so correct me if I'm wrong here. Also it seems atomic_add_rel_32(&mp_naps, 1) doesn't increase mp_naps and cpu_mp_start() of mp_machdep.c complaines with "WARNING: Some AP's failed to start" msg at boot. It could be related maybe because ACTLR smp bit is not set, since A20 CPU0/CPU1 status register reading says SMP mode is still not set. A20 doc is not good so I had to look for linux codes. Sysctl reading says: root@arm:~ # sysctl -a|grep cpu kern.sched.cpusetsize: 4 kern.ccpu: 1948 kern.smp.maxcpus: 4 kern.smp.cpus: 1 net.inet.tcp.per_cpu_timers: 0 debug.cpufreq.lowest: 0 debug.cpufreq.verbose: 0 hw.ncpu: 2 So am I missing something in my code or are there some places where I should put debug printf checking for variables, register values etc. ? I appreciate if someone can point me to the right direction. Boot log at: https://github.com/tsgan/allwinner_a10/blob/master/a20/dmesg_smp.txt thanks a lot, Ganbold