Date: Tue, 04 Feb 1997 21:37:20 +0800 From: Peter Wemm <peter@spinner.dialix.com> To: "John S. Dyson" <toor@dyson.iquest.net> Cc: michaelh@cet.co.jp (Michael Hancock), freebsd-smp@freebsd.org Subject: Re: [?] TLB Flushing on Context Switch PPro vs. Pentium Message-ID: <199702041337.VAA15405@spinner.DIALix.COM> In-Reply-To: Your message of "Tue, 04 Feb 1997 06:47:52 EST." <199702041147.GAA05042@dyson.iquest.net>
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"John S. Dyson" wrote: > > The PPro doesn't automatically flush the TLB on context switch like the > > Pentium did. What else does the PPro do differently? > > > On the non-SMP kernel, we specifically set the PG_G flag that > keeps the kernel pages in the TLB on PPro. I have also been > playing with the idea of using 4MB pages (which the P5 also > unofficially supports.) > > John The PPro also flushes something in it's pipelines and/or prefetch during context switch (ie: reload %cr3) while the P5 does not. We got bitten with this with a bug in the startup code when we first tried it on a P6. The code basically was: movl $_PTD,%eax movl %eax,%cr3 jmp new_address The problem was that the 2nd cpu was running with a 4MB mapping at address 0 with Virtual == Physical at that stage. When going into full virtual mode, it loaded up the PTD pointer and jumped into the real location of the kernel.. But doing so also removed the P=V at 0, so the code disappeared right underneath the flow of execution. The P5 didn't care, it obviously had enough in it's pipeline to keep going, but the P6 spat the dummy (as should happen on all cpu's, or bugs like the above code go unnoticed). Cheers, -Peter
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